RF power amplifiers with improved efficiency and output power

• US 8,686,796 B2
• Filed: 04/19/2011
• Issued: 04/01/2014
• Est. Priority Date: 04/19/2011
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Presti, Calogero D.
• Primary Examiner(s): Nguyen, Khanh V
• Application Number:
  US13/090,054
• Publication Number:
  US 20120268205A1
• Time in Patent Office: 1,078 Days
• Field of Search: 330/195, 330/277, 330/253, 330/302, 330/311
• US Class Current: 330/311
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/523 for amplifiers using field-effect devices H03F1/526 takes precedence
• CPC Class Codes: H03F 2203/45296 the AAC comprising one or more discrete capacitive elements, e.g. a transistor coupled as capacitor
• CPC Class Codes: H03F 2203/45301 there are multiple cascaded folded or not folded common gate stages of a cascode dif amp
• CPC Class Codes: H03F 2203/45311 the common gate stage of a cascode dif amp being implemented by multiple transistors
• CPC Class Codes: H03F 2203/45731 the LC comprising a transformer
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence

Abstract

Amplifiers with improved efficiency and output power are described. In an exemplary design, an apparatus includes an amplifier having at least three transistors and at least two capacitors. The at least three transistors are coupled in a stack and receive and amplify an input signal and provide an output signal. The at least two capacitors include at least one capacitor coupled between the drain and source of an associated transistor for each of at least two transistors in the stack, e.g., at least one capacitor for each transistor in the stack except for the bottommost transistor in the stack. The at least two capacitors recycle energy from gate-to-source parasitic capacitors of the at least two transistors to the output signal, which improves efficiency and output power of the amplifier.

Claims

1. An apparatus comprising:

an amplifier comprising;

at least three transistors coupled in a stack and configured to receive and amplify an input signal and provide an output signal; and

a first capacitor coupled between a drain and a source of a first transistor in the stack and a second capacitor coupled between a drain and a source of a second transistor in the stack, wherein a third transistor in the stack is controlled by the input signal and excludes a capacitor between a drain and source of the third transistor.

2. The apparatus of claim 1, at least one of the first and second capacitors recycling energy from gate-to-source parasitic capacitors of the first and second transistors to the output signal.

3. The apparatus of claim 1, the first and second capacitors for the first and second transistors in the stack comprising parasitic metal capacitances.

4. The apparatus of claim 1, the at least three transistors comprising the first transistor, the second transistor, and a third transistor, the third transistor having a source coupled to circuit ground and a drain coupled to a source of the second transistor, and the second transistor having a drain coupled to a source of the first transistor.

5. The apparatus of claim 4, the third transistor receiving the input signal, and the first transistor providing the output signal.

6. The apparatus of claim 1, the at least three transistors comprising metal oxide semiconductor (MOS) transistors.

7. The apparatus of claim 1, the amplifier further comprising:

at least one capacitor coupled to a gate of an associated transistor for each of the at least two transistors in the stack.

8. The apparatus of claim 1, the amplifier comprising a power amplifier to receive an input radio frequency (RF) signal and provide an output RF signal.

9. The apparatus of claim 8, further comprising:

an antenna coupled to the power amplifier and to transmit the output RF signal.

10. The apparatus of claim 1, the amplifier further comprising:

at least three second transistors coupled in a second stack and configured to receive and amplify a second input signal and provide a second output signal; and

at least one second capacitor coupled between a drain and a source of an associated second transistor for each of at least two second transistors in the second stack.

11. The apparatus of claim 10, the amplifier comprising a differential amplifier,

the input signal and the second input signal forming a differential input signal, and the output signal and the second output signal forming a differential output signal.

12. The apparatus of claim 10, further comprising:

a transformer coupled to a topmost transistor in the stack and a topmost second transistor in the second stack and to provide a single-ended output signal.

13. An integrated circuit comprising:

an amplifier comprising;

at least three metal oxide semiconductor (MOS) transistors coupled in a stack and configured to receive and amplify an input radio frequency (RF) signal and provide an output RF signal; and

a first capacitor coupled between a drain and a source of a first MOS transistor in the stack and a second capacitor coupled between a drain and a source of a second MOS transistor in the stack, wherein a third MOS transistor in the stack is controlled by the input RF signal and excludes a capacitor between a drain and source of the third MOS transistor.

14. The integrated circuit of claim 13, the at least three MOS transistors comprising N-channel MOS (NMOS) transistors.

15. A method of performing signal amplification, comprising:

amplifying an input signal with at least three transistors coupled in a stack to obtain an output signal; and

bypassing at least two transistors in the stack with a first capacitor coupled between a drain and a source of a first transistor of the at least two transistors and a second capacitor coupled between a drain and a source of a second transistor of the at least two transistors, wherein a third transistor in the stack is controlled by the input signal and excludes a capacitor between a drain and source of the third transistor.

16. An apparatus comprising:

means for amplifying an input signal to obtain an output signal, the means for amplifying comprising at least three transistors coupled in a stack; and

means for bypassing at least two transistors in the stack, the means for bypassing comprising a first capacitor coupled between a drain and a source of a first transistor of the at least two transistors and a second capacitor coupled between a drain and a source of a second transistor of the at least two transistors, wherein a third transistor in the stack is controlled by the input signal and excludes a capacitor between a drain and source of the third transistor.