Inductor structure

• US 8,686,821 B2
• Filed: 06/19/2012
• Issued: 04/01/2014
• Est. Priority Date: 01/19/2012
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Chang, Yung-Chung, Chen, Meng-Sheng, Liu, Chang-Chih, Chang, Li-Chi, Tsai, Cheng-Hua
• Primary Examiner(s): Talpalatski, Alexander
• Assistant Examiner(s): LIAN, MANG TIN BIK
• Application Number:
  US13/526,534
• Publication Number:
  US 20130187743A1
• Time in Patent Office: 651 Days
• Field of Search: 336/200, 336/223, 336/145, 336/182, 336/220, 336/170
• US Class Current: 336/147
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/004 with the coil helically wound around an axis without a core

Abstract

An inductor structure including a plurality of solenoids and at least one connecting line is provided. One of the solenoids serves as a core, and the remaining solenoids are sequentially wound around the core solenoid. Axes of the solenoids are substantially directed to the same direction. Each connecting line is correspondingly connected between ends of two adjacent solenoids to serially connect the solenoids.

Claims

1. An inductor structure comprising:

a plurality of solenoids, one of the solenoids serving as a core, the remaining solenoids being sequentially wound around the core solenoid, axes of the plurality of solenoids being substantially directed to a same direction; and

at least one connecting line, each of the at least one connecting line being correspondingly connected between ends of two adjacent solenoids to serially connect the plurality of solenoids,

the inductor structure being constructed in a multi-layer circuit board,

wherein the axes of the solenoids are parallel to a planar direction of the multi-layer circuit board,

wherein the multi-layer circuit board comprises N circuit layers and a plurality of dielectric layers located among the circuit layers, the number of the solenoids is M, and M is greater than 1 and smaller than or substantially equal to N/2, and

wherein the circuit layers are sequentially arranged from a first circuit layer to an N^th circuit layer along a direction, the solenoids are arranged inside out from a first solenoid to an M^th solenoid, and each of the solenoids is represented as;

an (i)^th solenoid comprising;

a plurality of (a_i)^th conductive lines located in an (a_i)^th circuit layer of the circuit layers;

a plurality of (b_i)^th conductive lines located in a (b_i)^th circuit layer of the circuit layers; and

a plurality of (i)^th conductive vias, each of the (i)^th conductive vias passing through all of the dielectric layers among the (a_i)^th circuit layer and the (b_i)^th circuit layer and connecting the corresponding (a_i)^th conductive lines and the corresponding (b₁)^th conductive lines to form the (i)th solenoid, wherein i is an integer ranging from 1 to M, a_i and b_i are integers ranging from 1 to N, a_i<

b_i, a₁>

a₂ . . . >

a_M, and b₁<

b₂ . . . b_M-1<

b_M.

2. The inductor structure as recited in claim 1, wherein the axes of the solenoids are coincided with one another.

3. The inductor structure as recited in claim 1, wherein i=1, and a dielectric layer of the dielectric layers located between the a₁ circuit layer and the b₁ circuit layer of the circuit layers is a core layer of the multi-layer circuit board.

4. The inductor structure as recited in claim 1, wherein the multi-layer circuit board is a printed circuit board, a ceramic circuit board, a chip, or an interposer.