Semiconductor device and structure

• US 8,687,399 B2
• Filed: 10/02/2011
• Issued: 04/01/2014
• Est. Priority Date: 10/02/2011
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Sekar, Deepak C, Or-Bach, Zvi, Lim, Paul
• Primary Examiner(s): DINH, SON T
• Application Number:
  US13/251,271
• Publication Number:
  US 20130083587A1
• Time in Patent Office: 912 Days
• Field of Search: 365/51, 365/63, 365/174, 365/222, 257/48, 257/103
• US Class Current: 365/51
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 27/0203 Particular design considerations for integrated circuits
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12033 : Gunn diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H10B 12/05 : Making the transistor
• CPC Class Codes: H10B 12/09 : with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures

Abstract

An Integrated device comprising a first monocrystalline layer comprising logic circuit regions and a second monocrystalline layer comprising memory regions constructed above first monocrystalline layer, wherein the memory regions comprise second transistors, wherein said second transistors comprise drain and source that are horizontally oriented with respect to the second monocrystalline layer, and a multiplicity of vias through the second monocrystalline layer providing connections between the memory regions and the logic circuit regions, wherein at least one of the multiplicity of vias have a radius of less than 100 nm.

Claims

1. An Integrated device, comprising;

a first monocrystalline layer comprising memories;

wherein said memories comprise an interconnection layer comprising copper or aluminum, and

a second layer comprising second transistors overlaying said interconnection layer,

wherein said second transistors are horizontally oriented monocrystalline transistors, and

wherein a plurality of vias through said second layer provide connections between said memories and said second transistors, and

wherein at least one of said plurality of vias has a radius of less than 100 nm.

2. A system comprising an Integrated device according to claim 1.

3. The Integrated device according to claim 1,

wherein said memories are controlled by decoder logic, said decoder logic comprises said second transistors.

4. The Integrated device according to claim 1,

wherein said memories comprise DRAM cells.

5. The Integrated device according to claim 1, further comprising:

memory management circuits, wherein said memory management circuits extend the useable endurance of said memories.

6. The Integrated device according to claim 1,

wherein said memories are volatile memories, and

wherein said second layer comprises non-volatile memories.

7. The Integrated device according to claim 1, wherein said device comprises a first integrated device and a second integrated device, and

wherein said first and second integrated devices are substantially different, and

wherein a majority of said first and second integrated device layers are substantially the same.

8. The Integrated device according to claim 1, further comprising:

refresh circuits for said memories,

wherein said refresh circuits allow a refresh to be done while avoiding interference with operation of said memories.

9. The Integrated device according to claim 1,

wherein said memories are non-volatile memories, and

wherein said second layer comprises volatile memories.

10. An Integrated device, comprising;

a first monocrystalline layer comprising memories;

wherein said memories comprise an interconnection layer comprising copper or aluminum, and

a second layer comprising second transistors overlaying said interconnection layer;

wherein said second transistors are horizontally oriented monocrystalline transistors, and

refresh circuits for said memories,

wherein said refresh circuits allow a refresh to be done while avoiding interference with operation of said memories.

11. A system comprising an Integrated device according to claim 10.

12. The Integrated device according to claim 10,

wherein said memories are controlled by decoder logic, said decoder logic comprises said second transistors.

13. The Integrated device according to claim 10,

wherein said memories comprise DRAM cells.

14. The Integrated device according to claim 10, further comprising:

memory management circuits, wherein said memory management circuits extend the useable endurance of said memories.

15. The Integrated device according to claim 10,

wherein said memories are volatile memories, and

wherein said second layer comprises non-volatile memories.

16. The Integrated device according to claim 10, wherein said device comprises a first integrated device and a second integrated device, and

wherein said first and second integrated devices are substantially different, and

wherein a majority of said first and second integrated device layers are substantially the same.

17. The Integrated device according to claim 10, further comprising:

a plurality of vias through said second layer providing connections between said memories and said second transistors,

wherein at least one of said plurality of vias has a radius of less than 100 nm.

18. The Integrated device according to claim 10,

wherein said memories are non-volatile memories, and

wherein said second layer comprises volatile memories.

19. The Integrated device according to claim 10,

wherein at least one of said memories comprises two ports, and comprises refresh logic to refresh at least one cell of said memory using one of said ports.

20. An Integrated device, comprising;

a first monocrystalline layer comprising first transistors;

an interconnection layer comprising copper or aluminum overlaying said first transistors, and

a second layer comprising second transistors overlaying said interconnection layer,

wherein said second transistors are horizontally oriented monocrystalline transistors, and

wherein a plurality of said second transistors form memories, and a plurality of vias through said second layer providing connections between said memories and said first transistors,

wherein at least one of said plurality of vias has a radius of less than 100 nm.

21. A system comprising an Integrated device according to claim 20.

22. The Integrated device according to claim 20,

wherein said memories are controlled by decoder logic, said decoder logic comprises said second transistors.

23. The Integrated device according to claim 20,

wherein said memories comprise DRAM cells.

24. The Integrated device according to claim 20, further comprising:

memory management circuits, wherein said memory management circuits extend the useable endurance of said memories.

25. The Integrated device according to claim 20,

wherein said memories are volatile memories, and

wherein said first layer comprises non-volatile memories.

26. The Integrated device according to claim 20, wherein said device comprises a first integrated device and a second integrated device, and

wherein said first and second integrated devices are substantially different, and

wherein a majority of said first and second integrated device layers are substantially the same.

27. The Integrated device according to claim 20, further comprising:

refresh circuits for said memories,

wherein said refresh circuits allow the refresh to be done while avoiding interference with operation of said memories.

28. The Integrated device according to claim 20,

wherein said memories are non-volatile memories, and

wherein said first layer comprises volatile memories.

29. The Integrated device according to claim 20,

wherein at least one of said memories comprises two ports, and comprises refresh logic to refresh at least one cell of said memories using one of said ports.

30. The Integrated device according to claim 20 wherein at least one of said second transistors is one of:

(i) a replacement gate transistor;

(ii) a recessed channel transistor (RCAT);

(iii) a side-gated transistor;

(iv) a junction-less transistor;

or

(v) a dopant-segregated Schottky Source Drain Transistor.