Semiconductor memory device
First Claim
1. A semiconductor memory device comprising:
- a first memory macro;
a second memory macro;
a first power switch coupled in common to the first and second memory macros to receive a control signal turning on the first power switch;
a second power switch coupled in common to the first and second memory macros to receive another control signal turning on the second power switch,wherein the first memory macro comprises a first memory cell and a first peripheral circuit, and the second memory macro comprises a second memory cell and a second peripheral circuit, andthe semiconductor memory device further comprises a third switch coupled in common to the first and second memory cells to receive a signal turning on the first and second memory cells.
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Accused Products
Abstract
A semiconductor memory device pertaining to the present invention includes a plurality of memory macros having memory cells and memory peripheral circuits which drive the memory cells; first power supply switches which control power supply to the memory cells; and a second power supply switch which controls power supply to the memory peripheral circuits. The first power supply switches are located within the memory macros, respectively, and provided between a power supply line feeding power to the memory cells and the memory cells. The second power supply switch is located outside the memory macros and provided between the power supply line and a common power supply wiring for the memory peripheral circuits in the plurality of memory macros.
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Citations
8 Claims
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1. A semiconductor memory device comprising:
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a first memory macro; a second memory macro; a first power switch coupled in common to the first and second memory macros to receive a control signal turning on the first power switch; a second power switch coupled in common to the first and second memory macros to receive another control signal turning on the second power switch, wherein the first memory macro comprises a first memory cell and a first peripheral circuit, and the second memory macro comprises a second memory cell and a second peripheral circuit, and the semiconductor memory device further comprises a third switch coupled in common to the first and second memory cells to receive a signal turning on the first and second memory cells. - View Dependent Claims (2, 3, 5, 6, 7, 8)
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4. A semiconductor memory device comprising:
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a first memory macro; a second memory macro; a first power switch coupled in common to the first and second memory macros to receive a control signal turning on the first power switch; a second power switch coupled in common to the first and second memory macros to receive another control signal turning on the second power switch, wherein the first memory macro comprises a first memory cell and a first peripheral circuit, and the second memory macro comprises a second memory cell and a second peripheral circuit, and the semiconductor memory device further comprises a third switch coupled to the first memory cell, and a fourth switch coupled to the second memory cell.
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Specification