Method and system for split voltage domain transmitter circuits

• US 8,687,981 B2
• Filed: 09/11/2008
• Issued: 04/01/2014
• Est. Priority Date: 10/02/2007
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Luxtera Incorporated (Cisco Systems, Inc.)
• Inventors: Welch, Brian, Kucharski, Daniel
• Primary Examiner(s): Stultz, Jessica
• Assistant Examiner(s): King, Joshua
• Application Number:
  US12/208,650
• Publication Number:
  US 20090087196A1
• Time in Patent Office: 2,028 Days
• Field of Search: 398/202, 398/208, 398/209, 398/210, 455/343.1, 455/341, 375/247, 375/297, 375/318, 375/319, 372/38.02, 372/38.07, 330/124.R
• US Class Current: 398/202
• CPC Class Codes: G02B 6/4201 Packages, e.g. shape, construction, internal or external details
• CPC Class Codes: G02B 6/4242 Mounting of the optical light guide to the lid of the package
• CPC Class Codes: H04B 10/501 Structural aspects
• CPC Class Codes: H04B 10/516 Details of coding or modulation
• CPC Class Codes: H04B 10/564 Power control
• CPC Class Codes: H04B 10/60 Receivers
• CPC Class Codes: H04B 10/693 Arrangements for optimizing the preamplifier in the receiver
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296

Abstract

Methods and systems for split voltage domain transmitter circuits are disclosed and may include amplifying a received signal in a plurality of partial voltage domains. Each of the partial voltage domains may be offset by a DC voltage from the other partial voltage domains. A sum of the plurality of partial domains may be equal to a supply voltage of the integrated circuit. A series of diodes may be driven in differential mode via the amplified signals. An optical signal may be modulated via the diodes, which may be integrated in a Mach-Zehnder or a ring modulator. The amplified signals may be communicated to the diodes, connected in a distributed configuration, via even-mode coupled transmission lines. The partial voltage domains may be generated via stacked source follower or emitter follower circuits. The voltage domain boundary value may be at one half the supply voltage due to symmetric stacked circuits.

Claims

1. A method for processing signals, the method comprising:

in an integrated circuit comprising a transmission line driver;

amplifying a received signal in a plurality of partial voltage domains;

generating said partial voltage domains in a domain splitter in said transmission line driver wherein each of said partial voltage domains is offset by a DC voltage from other of said partial voltage domains and wherein a sum of said plurality of partial domains is equal to a supply voltage of said integrated circuit; and

controlling a voltage domain boundary value between two partial voltage domains utilizing a differential amplifier that samples an output voltage of a cascade amplifier that is an input to the transmission line driver and controls a current supplying said cascade amplifier.

2. The method according to claim 1, comprising driving a series of diodes in differential mode via said amplified signals.

3. The method according to claim 2, comprising modulating an optical signal via said diodes.

4. The method according to claim 2, wherein said diodes are integrated in a Mach-Zehnder modulator.

5. The method according to claim 2, wherein said diodes are integrated in a ring modulator.

6. The method according to claim 2, wherein said diodes are connected in a distributed configuration.

7. The method according to claim 2, comprising communicating said amplified signals to said diodes via transmission lines.

8. The method according to claim 7, wherein said transmission lines are even-mode coupled.

9. The method according to claim 1, comprising generating said partial voltage domains via stacked source follower circuits.

10. The method according to claim 1, comprising generating said partial voltage domains via stacked emitter follower circuits.

11. The method according to claim 1, comprising generating said voltage domain boundary value of one half the supply voltage via symmetric stacked circuits.

12. A system for processing signals, the system comprising:

one or more circuits in an integrated circuit comprising a transmission line driver, said one or more circuits operable to;

amplify a received signal in a plurality of partial voltage domains;

generate said partial voltage domains in a domain splitter in said transmission line driver, wherein each of said partial voltage domains is offset by a DC voltage from other said partial voltage domains and wherein a sum of said plurality of partial domains is equal to a supply voltage of said integrated circuit; and

control a voltage domain boundary value between two partial voltage domains utilizing a differential amplifier that samples an output voltage of a cascade amplifier that is an input to the transmission line driver and controls a current supplying said cascade amplifier.

13. The system according to claim 12, wherein said one or more circuits drives a series of diodes in differential mode via said amplified signals.

14. The system according to claim 13, wherein said one or more circuits modulates an optical signal via said diodes.

15. The system according to claim 13, wherein said diodes are integrated in a Mach-Zehnder modulator.

16. The system according to claim 13, wherein said diodes are integrated in a ring modulator.

17. The system according to claim 13, wherein said diodes are connected in a distributed configuration.

18. The system according to claim 13, wherein said one or more circuits communicates said amplified signals to said diodes via transmission lines.

19. The system according to claim 18, wherein said transmission lines are even-mode coupled.

20. The system according to claim 12, wherein said one or more circuits generates said partial voltage domains via stacked source follower circuits.

21. The system according to claim 12, wherein said one or more circuits generates said partial voltage domains via stacked emitter follower circuits.

22. The system according to claim 12, wherein said one or more circuits generates said voltage domain boundary value of one half the supply voltage via symmetric stacked circuits.