Integrated circuit test optimization using adaptive test pattern sampling algorithm

• US 8,689,066 B2
• Filed: 06/29/2011
• Issued: 04/01/2014
• Est. Priority Date: 06/29/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Grady, Matthew S., Johnson, Mark C., Pepper, Bradley D., Percy, Dean G., Pranys, Joseph C.
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US13/172,179
• Publication Number:
  US 20130007546A1
• Time in Patent Office: 1,007 Days
• Field of Search: 714/726, 714/33, 714/745, 714/728
• US Class Current: 714/728
• CPC Class Codes: G01R 31/31835 Analysis of test coverage or failure detectability
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers

Abstract

A method of implementing integrated circuit device testing includes performing baseline testing of a first group of chips using a full set of test patterns, and for chip identified as failing, determining, a score for each test pattern in the full set. The score is indicative of an ability of the test pattern to uniquely identify a failing chip with respect to other test patterns. Following the baseline testing, streamlined testing on a second group of chips is performed, using a reduced set of the test patterns having highest average scores as determined by the baseline testing. Following the streamlined testing, full testing on a third group of chips is performed using the full set of test patterns, and updating the average score for each pattern. Further testing alternates between the streamlined testing and the full testing for additional groups of chips.

Claims

1. A method of implementing integrated circuit device testing using adaptive test pattern selection, the method comprising:

performing an initial baseline testing of a first group of chips to be tested using a full set of test patterns;

for each of the first group of chips identified as failing at least one of the full set of test patterns, determining, by a computing device, a score for each test pattern in the full set, the score indicative of an ability of the test pattern to uniquely identify a failing chip with respect to other test patterns, and keeping a running average of the score for each test pattern as subsequent failed chips are identified;

following the initial baseline testing, performing streamlined testing on a second group of chips for a first duration, the streamlined testing comprising using a reduced set of the test patterns, the reduced set comprising test patterns having highest scores as determined by the initial baseline testing;

following the streamlined testing, performing full testing on a third group of chips for a second duration, the full testing comprising using the full set of the test patterns and, during the full testing, resuming determining a score for each test pattern in the full set for each failing device in the third group of chips and updating the running average of the score for each test pattern; and

alternating between the streamlined testing and the full testing for additional groups of chips.

2. The method of claim 1, wherein the score for each test pattern is determined as follows:

Score_fail=total patterns+1−

(# of failing patterns); and

Score pass=0;

wherein, for each failing chip identified during the initial baseline testing and the full testing, Score_fail represents the score for each test pattern in the full set that was failed by the failing chip and Score_pass represents the score for each test pattern in the full set that was not failed by the failing chip.

3. The method of claim 2, wherein the reduced set of the test patterns is about 50% of the full set of test patterns.

4. The method of claim 2, wherein the first duration is greater than the second duration.

5. The method of claim 4, wherein the first duration and the second duration are selected so as to establish a duty cycle of testing about 80% of chips under streamlined testing and about 20% of chips under full testing.

6. The method of claim 2, further comprising detecting a reset criteria based on a defined event that results in restarting the initial baseline testing by erasing a current test pattern ranking.

7. The method of claim 6, wherein the defined event comprises one or more of:

reaching a defined count of failing chips, detecting a change in observed yield, and reaching a beginning of a new lot of wafers.

8. A computer program product comprising a non-transitory, tangible computer readable medium having computer readable instructions stored thereon that, when executed by a computer, implement a method of testing an integrated circuit device by using adaptive test pattern selection, the method comprising:

performing an initial baseline testing of a first group of chips to be tested using a full set of test patterns;

for each of the first group of chips identified as failing at least one of the full set of test patterns, determining a score for each test pattern in the full set, the score indicative of an ability of the test pattern to uniquely identify a failing chip with respect to other test patterns, and keeping a running average of the score for each test pattern as subsequent failed chips are identified;

following the initial baseline testing, performing streamlined testing on a second group of chips for a first duration, the streamlined testing comprising using a reduced set of the test patterns, the reduced set comprising test patterns having highest scores as determined by the initial baseline testing;

following the streamlined testing, performing full testing on a third group of chips for a second duration, the full testing comprising using the full set of the test patterns and, during the full testing, resuming determining a score for each test pattern in the full set for each failing device in the third group of chips and updating the running average of the score for each test pattern; and

alternating between the streamlined testing and the full testing for additional groups of chips.

9. The computer program product of claim 8, wherein the score for each test pattern is determined as follows:

Score_fail=total patterns+1−

(# of failing patterns); and

Score_pass=0;

wherein, for each failing chip identified during the initial baseline testing and the full testing, Score_fail represents the score for each test pattern in the full set that was failed by the failing chip and Score_pass represents the score for each test pattern in the full set that was not failed by the failing chip.

10. The computer program product of claim 9, wherein the reduced set of the test patterns is about 50% of the full set of test patterns.

11. The computer program product of claim 9, wherein the first duration is greater than the second duration.

12. The computer program product of claim 11, wherein the first duration and the second duration are selected so as to establish a duty cycle of testing about 80% of chips under streamlined testing and about 20% of chips under full testing.

13. The computer program product of claim 9, wherein the method further comprises detecting a reset criteria based on a defined event that results in restarting the initial baseline testing by erasing a current test pattern ranking.

14. The computer program product of claim 13, wherein the defined event comprises one or more of:

reaching a defined count of failing chips, detecting a change in observed yield, and reaching a beginning of a new lot of wafers.

15. A system for implementing integrated circuit device testing using adaptive test pattern selection, comprising:

a computing network including a processing device in communication with one or more computer memory storage devices; and

the processing device configured to;

perform an initial baseline testing of a first group of chips to be tested using a full set of test patterns;

for each of the first group of chips identified as failing at least one of the full set of test patterns, determine a score for each test pattern in the full set, the score indicative of an ability of the test pattern to uniquely identify a failing chip with respect to other test patterns, and keeping a running average of the score for each test pattern as subsequent failed chips are identified;

following the initial baseline testing, perform streamlined testing on a second group of chips for a first duration, the streamlined testing comprising using a reduced set of the test patterns, the reduced set comprising test patterns having highest scores as determined by the initial baseline testing;

following the streamlined testing, perform full testing on a third group of chips for a second duration, the full testing comprising using the full set of the test patterns and, during the full testing, resume determining a score for each test pattern in the full set for each failing device in the third group of chips and updating the running average of the score for each test pattern; and

alternate between the streamlined testing and the full testing for additional groups of chips.

16. The system of claim 15, wherein the score for each test pattern is determined as follows:

Score_fail=total patterns+1−

(# of failing patterns); and

Score_pass=0;

wherein, for each failing chip identified during the initial baseline testing and the full testing, Score_fail represents the score for each test pattern in the full set that was failed by the failing chip and Score_pass represents the score for each test pattern in the full set that was not failed by the failing chip.

17. The system of claim 16, wherein the reduced set of the test patterns is about 50% of the full set of test patterns.

18. The system of claim 16, wherein the first duration and the second duration are selected so as to establish a duty cycle of testing about 80% of chips under streamlined testing and about 20% of chips under full testing.

19. The system of claim 16, wherein the processing device is further configured to detect a reset criteria based on a defined event that results in restarting the initial baseline testing by erasing a current test pattern ranking.

20. The system of claim 19, wherein the defined event comprises one or more of:

reaching a defined count of failing chips, detecting a change in observed yield, and reaching a beginning of a new lot of wafers.