Method for manufacturing semiconductor device

• US 8,691,641 B2
• Filed: 05/07/2013
• Issued: 04/08/2014
• Est. Priority Date: 04/07/2010
• Status: Active Grant

• Current Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Original Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Inventors: Zhong, Huicai, Liang, Qingqing
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US13/888,930
• Publication Number:
  US 20130244393A1
• Time in Patent Office: 336 Days
• Field of Search: 438/197, 438/300, 257/E21.619, 257/E21.634, 257/E21.431
• US Class Current: 438/197
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method of manufacturing a semiconductor device is provided, in which after forming a gate stack and a first spacer thereof, a second spacer and a third spacer are formed; and then an opening is formed between the first spacer and the third spacer by removing the second spacer. The range of the formation for the raised active area 220 is limited by forming an opening 214 between the first spacer 208 and the third spacer 212. The raised active area 220 is formed in the opening 214 in a self-aligned manner, so that a better profile of the raised active area 220 may be achieved and the possible shorts between adjacent devices caused by an unlimited manner may be avoided. Moreover, based on such a manufacturing method, it is easy to make the gate electrode 204 to be flushed with the raised active area 220, and is also easy to implement the dual stress nitride process so as to increase the mobility of the device.

Claims

1. A method of manufacturing a semiconductor device, comprising steps of:

A. providing a semiconductor substrate;

B. forming a gate stack on the semiconductor substrate, and forming a first spacer on sidewalls of the gate stack;

C. forming a second sidewall spacer on sidewalls of the first spacer, and forming a third spacer on sidewalls of the second spacer, wherein the second sidewall spacer is formed between the first and third sidewalls spacers;

D. removing the second spacer to form an opening;

E. etching the semiconductor substrate through the opening to form a cavity within the semiconductor substrate;

F. forming an embedded active area in the cavity;

G. forming a raised active area within the opening; and

H. siliciding the semiconductor device to form a metal silicide layer.

2. The method according to claim 1, further comprising a step between step G and step H:

planarizing the semiconductor device to make the gate stack to be substantially flushed with the raised active area.

3. The method according to claim 1, further comprising a step after step H:

removing the third spacer and parts of the first spacer, and forming a stress nitride layer to cover the semiconductor device.

4. The method according to claim 1, wherein the first spacer, the third spacer and a gate cap are each formed of a nitride material.

5. The method according to claim 1, wherein the second spacer is formed of an oxide material.

6. The method according to claim 2, wherein the first spacer, the third spacer and a gate cap are each formed of a nitride material.

7. The method according to claim 3, wherein the first spacer, the third spacer and a gate cap are each formed of a nitride material.

8. The method according to claim 2, wherein the second spacer is formed of an oxide material.

9. The method according to claim 3, wherein the second spacer is formed of an oxide material.