Controlled gas mixing for smooth sidewall rapid alternating etch process

• US 8,691,698 B2
• Filed: 02/08/2012
• Issued: 04/08/2014
• Est. Priority Date: 02/08/2012
• Status: Active Grant

• Current Assignee: Lam Research Corporation
• Original Assignee: Lam Research Corporation
• Inventors: Xu, Qing, Thie, William, Rusu, Camelia
• Primary Examiner(s): Vinh, Lan
• Assistant Examiner(s): Lu, Jiong-Ping
• Application Number:
  US13/369,125
• Publication Number:
  US 20130203256A1
• Time in Patent Office: 790 Days
• Field of Search: None
• US Class Current: 438/696
• CPC Class Codes: H01L 21/30655 comprising alternated and repeated etching and passivation steps, e.g. Bosch process
• CPC Class Codes: H01L 21/32137 of silicon-containing layers

Abstract

A method for etching features in a silicon layer disposed below a mask in a plasma processing chamber a plurality of cycles is provided. A deposition phase forming a deposition on the silicon layer in the plasma processing chamber is provided comprising providing a deposition gas into the plasma processing chamber wherein the deposition gas comprises a halogen containing etchant component and a fluorocarbon deposition component, forming the deposition gas into a plasma, which provides a net deposition on the silicon layer, and stopping the flow of the deposition gas. A silicon etch phase is provided, comprising providing a silicon etch gas into the plasma processing chamber that is different than the deposition gas, forming the silicon etch gas into a plasma to etch the silicon layer, and stopping the flow of the silicon etch gas.

Claims

1. A method for etching features in a silicon layer disposed below a mask in a plasma processing chamber, comprising a plurality of cycles, wherein each cycle comprises:

providing a deposition phase forming a deposition on the silicon layer in the plasma processing chamber, comprising;

providing a deposition gas into the plasma processing chamber wherein the deposition gas comprises a halogen containing etchant component and a fluorocarbon deposition component;

forming the deposition gas into a plasma, which provides a net deposition on the silicon layer; and

stopping the flow of the deposition gas; and

providing a silicon etch phase, comprising;

providing a silicon etch gas into the plasma processing chamber that is different than the deposition gas;

forming the silicon etch gas into a plasma to etch the silicon layer; and

stopping the flow of the silicon etch gas.

2. The method, as recited in claim 1, wherein the providing the deposition phase further comprises providing a bias of 50 to 300 volts.

12. The method, as recited in claim 1, wherein the halogen containing etchant is at least one of SF₆ or NF₃.

13. The method, as recited in claim 12, wherein the fluorocarbon deposition component comprise at least one of C₄F₈, or C₄F₆.

14. The method, as recited in claim 1, wherein the providing the etching phase further comprises providing a bias of 50 to 200 volts.

15. The method, as recited in claim 14, wherein the deposition phase bias is between 100 to 150 volts.

16. The method, as recited in claim 1, wherein the silicon etch phase provides a net removal of the deposition layer.

17. The method, as recited in claim 1, wherein a ratio of the halogen containing enchant to fluorocarbon deposition component ranges from 1:

20 to 1;

8.

18. The method, as recited in claim 1, wherein the plurality of cycles is between 100 to 600 cycles.

3. The method, as recited in 2, wherein the halogen of the halogen containing etchant component comprises at least one of fluorine, bromine, or chlorine.

4. The method, as recited in claim 3, wherein the halogen containing etchant is at least one of SF₆, CF₄, or NF₃.

5. The method, as recited in claim 4, wherein the fluorocarbon deposition component comprise at least one of C₄F₈, or C₄F₆.

6. The method, as recited in claim 5, wherein the providing the etching phase further comprises providing a bias of 50 to 200 volts.

7. The method, as recited in claim 6, wherein the deposition phase bias is between 100 to 150 volts.

8. The method, as recited in claim 7, wherein the silicon etch phase provides a net removal of the deposition layer.

9. The method, as recited in claim 8, wherein a ratio of the halogen containing enchant to fluorocarbon deposition component ranges from 1:

20 to 1;

8.

10. The method, as recited in claim 9, wherein the plurality of cycles is between 100 to 600 cycles.

11. The method, as recited in 1, wherein the halogen of the halogen containing etchant component comprises at least one of fluorine, bromine, or chlorine.

19. A method for etching features in a silicon layer disposed below a mask in a plasma processing chamber, comprising a plurality of cycles, wherein each cycle comprises:

providing a deposition phase forming a deposition on the silicon layer in the plasma processing chamber, comprising;

providing a deposition gas into the plasma processing chamber wherein the deposition gas comprises at least one of SF₆, CF₄, or NF₃ and at least one of C₄F₈, or C₄F₆;

providing a bias of 50 to 300 volts;

forming the deposition gas into a plasma, which provides a net deposition on the silicon layer; and

stopping the flow of the deposition gas; and

providing a silicon etch phase, comprising;

providing a silicon etch gas into the plasma processing chamber that is different than the deposition gas;

providing a bias of 50 to 200 volts;

forming the silicon etch gas into a plasma to etch the silicon layer; and

stopping the flow of the silicon etch gas.