Focal plane array processing method and apparatus
First Claim
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1. An apparatus comprising:
- a two-dimensional array of photodetectors; and
a two-dimensional array of analog-to-digital converters (ADCs), wherein at least one of the ADCs in the two-dimensional array of ADCs comprises;
a capacitor operably coupled to a photodetector in the two-dimensional array of photodetectors to integrate current from the photodetector;
a comparator operably coupled to an integration node of the capacitor to generate a latch signal when a voltage across the capacitor reaches a reference voltage; and
a charge subtraction circuit operably coupled to the integration node to subtract charge from the integration node after the comparator generates the latch signal, wherein the charge subtraction circuit comprises;
a charge-sharing capacitor; and
at least one switch to discharge the charge-sharing capacitor in response to a clock signal based on an output of the comparator.
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Abstract
A digital focal plane array includes an all-digital readout integrated circuit in combination with a detector array. The readout circuit includes unit cell electronics, orthogonal transfer structures, and data handling structures. The unit cell electronics include an analog to digital converter. Orthogonal transfer structures enable the orthogonal transfer of data among the unit cells. Data handling structures may be configured to operate the digital focal plane array as a data encryptor/decipherer. Data encrypted and deciphered by the digital focal plane array need not be image data.
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Citations
24 Claims
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1. An apparatus comprising:
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a two-dimensional array of photodetectors; and a two-dimensional array of analog-to-digital converters (ADCs), wherein at least one of the ADCs in the two-dimensional array of ADCs comprises; a capacitor operably coupled to a photodetector in the two-dimensional array of photodetectors to integrate current from the photodetector; a comparator operably coupled to an integration node of the capacitor to generate a latch signal when a voltage across the capacitor reaches a reference voltage; and a charge subtraction circuit operably coupled to the integration node to subtract charge from the integration node after the comparator generates the latch signal, wherein the charge subtraction circuit comprises; a charge-sharing capacitor; and at least one switch to discharge the charge-sharing capacitor in response to a clock signal based on an output of the comparator. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An apparatus comprising:
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a two-dimensional array of photodetectors; and a two-dimensional array of analog-to-digital converters (ADCs), wherein each ADC in the two-dimensional array of ADCs comprises; a capacitor operably coupled to a photodetector in the two-dimensional array of photodetectors to integrate current from the photo detector; a comparator operably coupled to an integration node of the capacitor to generate a latch signal when a voltage across the capacitor reaches a reference voltage; a charge subtraction circuit operably coupled to the integration node to subtract charge from the integration node after the comparator generates the latch signal; and a counter to latch a count value based on the latch signal; and n-bit column parallel connections between the counters. - View Dependent Claims (9, 10, 11, 12)
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13. A method of controlling charge in a pixel of a focal plane array, the method comprising:
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(A) producing a photocurrent with a photodetector in a two-dimensional array of photodetectors; (B) generating a voltage representing the photocurrent in a corresponding analog-to-digital converter (ADC) in a two-dimensional array of ADCs; (C) comparing the voltage to a reference voltage with a comparator included in the corresponding ADC so as to cause the comparator to emit a latch signal when the voltage reaches the reference voltage; and (D) subtracting charge from the comparator after the comparator emits the latch signal, wherein (D) further comprises discharging at least some of the charge from a charge-sharing capacitor in a charge-subtraction circuit. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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20. A method of controlling charge in a pixel of a focal plane array, the method comprising:
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(A) producing a photocurrent with a photodetector in a two-dimensional array of photodetectors; (B) generating a voltage representing the photocurrent in a corresponding analog-to-digital converter (ADC) in a two-dimensional array of ADCs; (C) comparing the voltage to a reference voltage with a comparator included in the corresponding ADC so as to cause the comparator to emit a latch signal when the voltage reaches the reference voltage; and (D) subtracting charge from the comparator after the comparator emits the latch signal, wherein (D) further comprises pulsing a charge subtraction circuit so as to cause the charge subtraction circuit to subtract additional charge from the comparator. - View Dependent Claims (21, 22, 23, 24)
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Specification