Focal plane array processing method and apparatus

• US 8,692,176 B2
• Filed: 11/18/2011
• Issued: 04/08/2014
• Est. Priority Date: 10/27/2006
• Status: Active Grant

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Kelly, Michael, Tyrrell, Brian, Colonero, Curtis, Berger, Robert, Schultz, Kenneth, Wey, James, Mooney, Daniel, Candell, Lawrence
• Primary Examiner(s): Luu, Thanh
• Assistant Examiner(s): Naphas, Renee
• Application Number:
  US13/299,995
• Publication Number:
  US 20120138774A1
• Time in Patent Office: 872 Days
• Field of Search: 250/208.1, 250/214.A, 257/292, 348/294, 348/308, 341155-158
• US Class Current: 250/208.1
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: G11B 20/00086 Circuits for prevention of unauthorised reproduction or copying, e.g. piracy indicating unauthorised use of record carriers in general G11B23/28; scrambling for television signal recording H04N5/913; network architectures or network protocols for network security H04L63/00; cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
• CPC Class Codes: G11B 20/0021 involving encryption or decryption of contents recorded on or reproduced from a record carrier
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 2209/805 Lightweight hardware, e.g. radio-frequency identification [RFID] or sensor
• CPC Class Codes: H04L 9/0631 Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
• CPC Class Codes: H04L 9/0637 Modes of operation, e.g. cipher block chaining [CBC], electronic codebook [ECB] or Galois/counter mode [GCM]
• CPC Class Codes: H04L 9/12 Transmitting and receiving encryption devices synchronised or initially set up in a particular manner
• CPC Class Codes: H04N 2005/91364 the video signal being scrambled
• CPC Class Codes: H04N 21/4223 Cameras H04N23/00 takes precedence
• CPC Class Codes: H04N 21/4408 involving video stream encryption, e.g. re-encrypting a decrypted video stream for redistribution in a home network
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 5/33 Transforming infrared radiation cameras or camera modules for generating image signals from infrared radiation H04N23/20; circuitry of SSIS for transforming infrared radiation into image signals H04N25/20
• CPC Class Codes: H04N 5/772 the recording apparatus and the television camera being placed in the same enclosure
• CPC Class Codes: H04N 5/913 for scrambling ; for copy protection

Abstract

A digital focal plane array includes an all-digital readout integrated circuit in combination with a detector array. The readout circuit includes unit cell electronics, orthogonal transfer structures, and data handling structures. The unit cell electronics include an analog to digital converter. Orthogonal transfer structures enable the orthogonal transfer of data among the unit cells. Data handling structures may be configured to operate the digital focal plane array as a data encryptor/decipherer. Data encrypted and deciphered by the digital focal plane array need not be image data.

Claims

1. An apparatus comprising:

a two-dimensional array of photodetectors; and

a two-dimensional array of analog-to-digital converters (ADCs), wherein at least one of the ADCs in the two-dimensional array of ADCs comprises;

a capacitor operably coupled to a photodetector in the two-dimensional array of photodetectors to integrate current from the photodetector;

a comparator operably coupled to an integration node of the capacitor to generate a latch signal when a voltage across the capacitor reaches a reference voltage; and

a charge subtraction circuit operably coupled to the integration node to subtract charge from the integration node after the comparator generates the latch signal, wherein the charge subtraction circuit comprises;

a charge-sharing capacitor; and

at least one switch to discharge the charge-sharing capacitor in response to a clock signal based on an output of the comparator.

2. The apparatus of claim 1, wherein the at least one ADC further comprises a counter to latch a count value based on the latch signal.

3. The apparatus of claim 2, further comprising a clock to generate a clock signal that determines a count rate of the counter.

4. The apparatus of claim 3, wherein the at least one ADC further comprises a frequency multiplier operably coupled to the comparator to multiply the clock signal.

5. The apparatus of claim 2, wherein the counter is a modulo M counter.

6. The apparatus of claim 1, wherein the at least one ADC further comprises an oscillator.

7. The apparatus of claim 1, wherein the comparator is configured to generate the latch signal by subtracting the voltage across the capacitor from the reference voltage.

8. An apparatus comprising:

a two-dimensional array of photodetectors; and

a two-dimensional array of analog-to-digital converters (ADCs), wherein each ADC in the two-dimensional array of ADCs comprises;

a capacitor operably coupled to a photodetector in the two-dimensional array of photodetectors to integrate current from the photo detector;

a comparator operably coupled to an integration node of the capacitor to generate a latch signal when a voltage across the capacitor reaches a reference voltage;

a charge subtraction circuit operably coupled to the integration node to subtract charge from the integration node after the comparator generates the latch signal; and

a counter to latch a count value based on the latch signal; and

n-bit column parallel connections between the counters.

9. The apparatus of claim 8, further comprising a clock to generate a clock signal that determines a count rate of the counter.

10. The apparatus of claim 9, wherein the at least one ADC further comprises a frequency multiplier operably coupled to the comparator to multiply the clock signal.

11. The apparatus of claim 8, wherein the counter is a modulo M counter.

12. The apparatus of claim 8, wherein the at least one ADC further comprises an oscillator.

13. A method of controlling charge in a pixel of a focal plane array, the method comprising:

(A) producing a photocurrent with a photodetector in a two-dimensional array of photodetectors;

(B) generating a voltage representing the photocurrent in a corresponding analog-to-digital converter (ADC) in a two-dimensional array of ADCs;

(C) comparing the voltage to a reference voltage with a comparator included in the corresponding ADC so as to cause the comparator to emit a latch signal when the voltage reaches the reference voltage; and

(D) subtracting charge from the comparator after the comparator emits the latch signal, wherein (D) further comprises discharging at least some of the charge from a charge-sharing capacitor in a charge-subtraction circuit.

14. The method of claim 13, wherein (C) further comprises directing photocurrent along a clamp path when the voltage exceeds a predetermined value.

15. The method of claim 13, further comprising latching a count in a bidirectional counter based on a latch signal from the comparator.

16. The method of claim 15, further comprising generating a clock signal that determines a count rate of the bidirectional counter.

17. The method of claim 16, wherein (C) further comprises:

(C1) multiplying a frequency of the clock signal to generate a frequency multiplied clock signal; and

(C2) clocking the comparator with the frequency multiplied clock signal.

18. The method of claim 17, wherein (C) further comprises adjusting the frequency multiplied clock signal based on an intensity of illumination detected by the photodetector.

19. The method of claim 13, wherein (C) comprises subtracting the voltage generated in (B) from the reference voltage.

20. A method of controlling charge in a pixel of a focal plane array, the method comprising:

(A) producing a photocurrent with a photodetector in a two-dimensional array of photodetectors;

(B) generating a voltage representing the photocurrent in a corresponding analog-to-digital converter (ADC) in a two-dimensional array of ADCs;

(C) comparing the voltage to a reference voltage with a comparator included in the corresponding ADC so as to cause the comparator to emit a latch signal when the voltage reaches the reference voltage; and

(D) subtracting charge from the comparator after the comparator emits the latch signal, wherein (D) further comprises pulsing a charge subtraction circuit so as to cause the charge subtraction circuit to subtract additional charge from the comparator.

21. The method of claim 20, further comprising latching a count in a bidirectional counter based on a latch signal from the comparator.

22. The method of claim 20, further comprising generating a clock signal that determines a count rate of the bidirectional counter.

23. The method of claim 22, wherein (C) further comprises:

(C1) multiplying a frequency of the clock signal to generate a frequency multiplied clock signal; and

(C2) clocking the comparator with the frequency multiplied clock signal.

24. The method of claim 23, wherein (C) further comprises adjusting the frequency multiplied clock signal based on an intensity of illumination detected by the photodetector.