Micro electronic device having CMOS circuit and MEMS resonator formed on common silicon substrate
First Claim
1. A micro electronic device, comprising:
- a silicon substrate having a hollow region;
a CMOS circuit formed on the silicon substrate; and
an MEMS resonator partially suspended above the hollow region and separated from the CMOS circuit by at least a second etching channel, wherein the second etching channel communicates with the hollow region and the MEMS resonator comprises;
a silicon layer;
a plurality of metallic layers disposed above the silicon layer; and
an isolation layer covering a portion of sidewalls of the silicon layer.
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Abstract
A method for fabricating a MEMS resonator is provided. A stacked main body including a silicon substrate, a plurality of metallic layers and an isolation layer is formed and has a first etching channel extending from the metallic layers into the silicon substrate. The isolation layer is filled in the first etching channel. The stacked main body also has a predetermined suspended portion. Subsequently, a portion of the isolation layer is removed so that a second etching channel is formed and the remained portion of the isolation layer covers an inner sidewall of the first etching channel. Afterwards, employing the isolation layer that covers the inner sidewall of the first etching channel as a mask, an isotropic etching process through the second etching channel is applied to the silicon substrate, thereby forming the MEMS resonator suspending above the silicon substrate. A micro electronic device is also provided.
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Citations
7 Claims
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1. A micro electronic device, comprising:
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a silicon substrate having a hollow region; a CMOS circuit formed on the silicon substrate; and an MEMS resonator partially suspended above the hollow region and separated from the CMOS circuit by at least a second etching channel, wherein the second etching channel communicates with the hollow region and the MEMS resonator comprises; a silicon layer; a plurality of metallic layers disposed above the silicon layer; and an isolation layer covering a portion of sidewalls of the silicon layer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification