Electronic apparatus having IC temperature control

• US 8,692,568 B2
• Filed: 10/03/2011
• Issued: 04/08/2014
• Est. Priority Date: 08/04/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kinsley, Tom
• Primary Examiner(s): TANG, MINH NHUT
• Application Number:
  US13/251,859
• Publication Number:
  US 20120019274A1
• Time in Patent Office: 918 Days
• Field of Search: None
• US Class Current: 324/750.03
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]

Abstract

The use of a power sink function in IC testing results in a simple and rapid method for testing ICs, and assembled modules, at elevated temperature profiles without the use of environmental ovens. Testing IC devices at elevated temperatures may be useful for ‘burn-in’, for ‘hot sort’ performance testing that may be used in electronic devices such as DRAM memory, logic, communication devices, and microprocessors. The power sink function may be implemented as an additional isolated area of active devices, or as a section of the circuit that is not involved in the testing procedure. Alternately, the power dissipation circuit may consist of a resistive path between two external pins that are not used for IC operation, where the resistor may be on the IC or on the package. This allows for control of the temperature level and profile by simple adjustment of the voltage between the two external pins.

Claims

1. An electronic apparatus comprising:

a memory array on a substrate, the substrate structured as an integrated circuit (IC) chip;

a heat generating circuit on the substrate;

a heater controller disposed on the substrate, the heater controller arranged to control the heat generating circuit; and

a mode register on the substrate, the mode register structured to provide input to the heater controller.

2. The electronic apparatus of claim 1, wherein the heat generating circuit is arranged separate from the memory array.

3. The electronic apparatus of claim 1, wherein the mode register includes a bit location allocated to store a bit indicative of a heat function disable or a heat function enable.

4. The electronic apparatus of claim 1, wherein the mode register includes a bit location allocated to store data indicative of a power level of a heat function.

5. The electronic apparatus of claim 1, wherein the mode register includes two bit locations allocated to store two bits to select the heat generating circuit or another heat generating circuit from a group of four heat generating circuits disposed on the substrate.

6. The electronic apparatus of claim 5, wherein the four heat generating circuits provide a 100 ohm power sink, a 200 ohm power sink, a 300 ohm power sink, and a 400 ohm power sink.

7. The electronic apparatus of claim 5, wherein the four heat generating circuits are controllable to use combinations of die termination circuitry on the substrate, based on settings in the mode register.

8. The electronic apparatus of claim 1, wherein the mode register includes a bit location allocated to store an indication of an on die termination level.

9. The electronic apparatus of claim 1, wherein the electronic apparatus includes an integrated sensor on the substrate coupled to a comparator on the substrate operable to compare an output of the integrated sensor to a stored temperature value.

10. The electronic apparatus of claim 1, wherein the temperature sensor is a diode junction.

11. An electronic apparatus comprising:

a memory array on a substrate, the substrate structured as an integrated circuit (IC) chip;

a heat generating circuit on the substrate;

a heater controller disposed on the substrate, the heater controller arranged to control the heat generating circuit;

a mode register on the substrate, the mode register structured to provide input to the heater controller; and

a timer circuit on the substrate, the timer circuit operable to control a time of operation of the heat generating circuit, the time correlated to a sensed temperature being lower than a stored temperature value.

12. The electronic apparatus of claim 11, wherein the electronic apparatus is arranged such that the heat generating circuit can be enabled during one or more of a normal operation of a functional circuit on the substrate other than the heat generating circuit and the heater controller, a test operation of the functional circuit, a reliability test operation, a burn-in operation, or a pre-heat period prior to normal operation of the functional circuit.

13. The electronic apparatus of claim 11, wherein the heat generating circuit includes memory cells such that the heat generating circuit is operable with the memory cells in an auto refresh mode.

14. The electronic apparatus of claim 11, wherein the electronic apparatus includes logic arranged to select the stored temperature value from a temperature profile stored on the substrate.

15. The electronic apparatus of claim 14, wherein the electronic apparatus is structured to operably store the temperature profile in the memory array.

16. The electronic apparatus of claim 11, wherein the substrate is a semiconductor substrate.

17. A method comprising:

determining a current temperature of a region on a substrate of an electronic apparatus, the substrate structured as an integrated circuit (IC) chip, the substrate having a memory array and a mode register disposed on the substrate;

controlling a heat generating circuit on the substrate from a heater controller, the heater controller disposed on the substrate and arranged to control the heat generating circuit based on input provided to the heater controller from the mode register; and

re-determining a new current temperature of the circuit.

18. The method of claim 17, wherein controlling the heat generating circuit includes operating the heat generating circuit in a heating mode if a stored temperature is greater than the current temperature.

19. The method of claim 18, wherein operating the heat generating circuit in the heating mode includes operating a power dissipation circuit at a predetermined operating rate and voltage.

20. The method of claim 19, wherein the stored temperature is a burn in temperature.

21. The method of claim 17, wherein determining the current temperature includes using an integrated temperature sensor on the substrate.

22. The method of claim 17, wherein the method includes storing a bit in the mode register to indicate enablement of the heat generating circuit.

23. The method of claim 17, wherein the method includes one or more of storing one or more bits in the mode register to indicate enablement of a power sink level of the heat generating circuit or storing one or more bits in the mode register to indicate selection of an on die termination level.

24. The method of claim 17, wherein includes controlling the heat generating circuit by operating memory cells of the memory array in an auto refresh mode to generate heat.

25. The method of claim 17, wherein the method includes electrically testing a circuit on the substrate in a selected temperature range controlled by the heater controller.