Circuit and method of driving the same

• US 8,692,579 B2
• Filed: 05/15/2012
• Issued: 04/08/2014
• Est. Priority Date: 05/19/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi
• Primary Examiner(s): TRAN, ANH Q
• Application Number:
  US13/471,625
• Publication Number:
  US 20120297219A1
• Time in Patent Office: 693 Days
• Field of Search: 326 93- 98
• US Class Current: 326/95
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H03K 19/0008 Arrangements for reducing power consumption
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits

Abstract

In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential.

Claims

1. A circuit comprising:

an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential corresponding to a result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal, the arithmetic circuit includes;

an arithmetic portion performing the logic operation processing,

a first field-effect transistor controlling whether a potential of the stored data is set at the potential corresponding to the result of the logic operation processing,

a second field-effect transistor controlling whether the potential of the stored data is set at a reference potential, and

a third field-effect transistor controlling whether the signal with a value corresponding to the stored data is output as the output signal,

wherein each of the first and second field-effect transistors, the third field-effect transistor, or each of the first to third field-effect transistors includes an oxide semiconductor layer including a channel formation region, and

wherein the oxide semiconductor layer includes a crystal aligned along a c-axis.

2. The circuit according to claim 1, wherein an off-state current per micrometer of channel width of each of the first and second field-effect transistors, the third field-effect transistor, or each of the first to third field-effect transistors is lower than or equal to 1×

10<sup>−

17</sup> A.

3. The circuit according to claim 1, wherein an off-state current per micrometer of channel width of each of the first and second field-effect transistors, the third field-effect transistor, or each of the first to third field-effect transistors is lower than or equal to 1×

10<sup>−

21</sup> A.

4. The circuit according to claim 1,

wherein the crystal has a triangular or hexagonal atomic arrangement when seen from a direction of an a-b plane, a surface, or an interface,

wherein the crystal has a layered arrangement of a metal atom along the c-axis or a layered arrangement of the metal atom and an oxygen atom along the c-axis, and

wherein a direction of an a-axis or a b-axis is varied in the a-b plane.

17. The circuit according to claim 1, wherein the oxide semiconductor layer contains indium.

18. A mobile information terminal comprising the circuit according to claim 1, wherein the mobile information terminal comprises a display portion.

5. A circuit comprising:

an arithmetic portion;

a first transistor;

a second transistor; and

a third transistor,

wherein one of a source electrode and a drain electrode of the first transistor is directly connected to the arithmetic portion,

wherein the other of the source electrode and the drain electrode of the first transistor is directly connected to one of a source electrode and a drain electrode of the second transistor, and

wherein the other of the source electrode and the drain electrode of the first transistor and the one of the source electrode and the drain electrode of the second transistor are electrically connected to one of a source electrode and a drain electrode of the third transistor,

wherein each of the first and second transistors, the third transistor, or each of the first to third field-effect transistors includes an oxide semiconductor layer including a channel formation region, and

wherein the oxide semiconductor layer includes a crystal aligned along a c-axis.

6. The circuit according to claim 5, wherein an off-state current per micrometer of channel width of each of the first and second transistors, the third transistor, or each of the first to third transistors is lower than or equal to 1×

10<sup>−

17</sup> A.

7. The circuit according to claim 5, wherein an off-state current per micrometer of channel width of each of the first and second transistors, the third transistor, or each of the first to third transistors is lower than or equal to 1×

10<sup>−

21</sup> A.

8. The circuit according to claim 5,

wherein the crystal has a triangular or hexagonal atomic arrangement when seen from a direction of an a-b plane, a surface, or an interface,

wherein the crystal has a layered arrangement of a metal atom along the c-axis or a layered arrangement of the metal atom and an oxygen atom along the c-axis, and

wherein a direction of an a-axis or a b-axis is varied in the a-b plane.

10. The circuit according to claim 5 further comprising an inverter,

wherein an input terminal of the inverter is directly connected to a node where the other of the source electrode and the drain electrode of the first transistor and the one of the source electrode and the drain electrode of the second transistor are connected, and

wherein an output terminal of the inverter is connected to the one of the source electrode and the drain electrode of the third transistor.

19. The circuit according to claim 5, wherein the oxide semiconductor layer contains indium.

20. A mobile information terminal comprising the circuit according to claim 5, wherein the mobile information terminal comprises a display portion.

9. A circuit comprising:

an arithmetic portion;

a first transistor;

a second transistor;

a third transistor; and

a fourth transistor,

wherein one of a source electrode and a drain electrode of the first transistor is directly connected to the arithmetic portion,

wherein the other of the source electrode and the drain electrode of the first transistor is directly connected to one of a source electrode and a drain electrode of the second transistor,

wherein the other of the source electrode and the drain electrode of the first transistor and the one of the source electrode and the drain electrode of the second transistor are electrically connected to one of a source electrode and a drain electrode of the third transistor, and

wherein the other of the source electrode and the drain electrode of the third transistor is directly connected to one of a source electrode and a drain electrode of the fourth transistor.

11. The circuit according to claim 9, wherein an off-state current per micrometer of channel width of each of the first and second transistors, the third transistor, or each of the first to third transistors is lower than or equal to 1×

10<sup>−

17</sup> A.

12. The circuit according to claim 9, wherein an off-state current per micrometer of channel width of each of the first and second transistors, the third transistor, or each of the first to third transistors is lower than or equal to 1×

10<sup>−

21</sup> A.

13. The circuit according to claim 9,

wherein each of the first and second transistors, the third transistor, or each of the first to third field-effect transistors includes an oxide semiconductor layer including a channel formation region, and

wherein the oxide semiconductor layer includes a crystal aligned along a c-axis.

14. The circuit according to claim 13,

wherein the crystal has a triangular or hexagonal atomic arrangement when seen from a direction of an a-b plane, a surface, or an interface,

wherein the crystal has a layered arrangement of a metal atom along the c-axis or a layered arrangement of the metal atom and an oxygen atom along the c-axis, and

wherein a direction of an a-axis or a b-axis is varied in the a-b plane.

15. The circuit according to claim 13, wherein the oxide semiconductor layer contains indium.

16. A mobile information terminal comprising the circuit according to claim 9, wherein the mobile information terminal comprises a display portion.