Power stage

• US 8,692,591 B2
• Filed: 10/26/2012
• Issued: 04/08/2014
• Est. Priority Date: 07/02/2009
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Acar, Mustafa, Nowak, Katarzyna
• Primary Examiner(s): JAGER, RYAN C
• Application Number:
  US13/661,275
• Publication Number:
  US 20130285713A1
• Time in Patent Office: 529 Days
• Field of Search: 327/112, 327/108, 327/110
• US Class Current: 327/112
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

A power stage has a differential output stage 2 driven by one or more buffer stages 4. The buffer stages 4 are implemented as high and low side buffers 12,14, each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS.

Claims

1. An apparatus, comprising:

an input circuit configured and arranged to provide a drive signal in response to receiving an input voltage;

a first set of isolation capacitive couplers provided with the drive signal from the input circuit;

at least one differential buffer stage, having a high side buffer stage and a low side buffer stage, configured and arranged to receive the drive signal from the first set of isolation capacitive couplers; and

an output stage, between a high voltage rail and a low voltage rail, configured and arranged to drive an isolation transformer through a second set of isolation capacitive couplers in response to the drive signal received from the at least one differential buffer stage.

2. The apparatus of claim 1, wherein the at least one differential buffer stage includes a first buffer stage having an inverting output that drives an inverting input of a second buffer stage.

3. The apparatus of claim 1, wherein the at least one differential buffer stage includes a self-biasing bias line connecting parallel ports of a first buffer stage and a second buffer stage and providing an intermediate voltage between the high side line and the low side line.

4. The apparatus of claim 1, wherein the input circuit is further configured and arranged between the low voltage rail and a digital power supply voltage.

5. The apparatus of claim 1, wherein the input circuit provides an input signal that includes a sinusoidal input voltage.

6. The apparatus of claim 1, wherein the at least one differential buffer stage includes a plurality of transistors which are each implemented with an isolated well.

7. The apparatus of claim 1, wherein the at least one differential buffer stage includes three buffer stages connected in series.

8. The apparatus of claim 1, wherein the at least one differential buffer stage includes a first buffer stage, a second buffer stage, and a third buffer stage connected in series, and an output of the third buffer stage is connected to an input of the output stage.

9. The apparatus of claim 1, further including a resistive network connected between the first set of isolation capacitive couplers and the at least one differential buffer stage.