Transceiver circuitry with multiple phase-locked loops
First Claim
1. An integrated circuit comprising:
- a first inductor-based phase-locked loop circuit having a first output, wherein the first phase-locked loop circuit generates a first control signal in a first frequency range at the first output;
a second inductor-based phase-locked loop circuit having a second output, wherein the second phase-locked loop circuit generates a second control signal in a second frequency range at the second output, wherein the first and second frequency ranges partially overlap with respect to one another, and wherein the first and second inductor-based phase-locked loop circuits operate at different frequencies when the first inductor-based phase-locked loop circuit is operated at a given frequency in the first frequency range that does not overlap with the second frequency range; and
interconnect circuitry coupled to the first and second outputs, wherein the interconnect circuitry receives the first control signal from the first output and receives the second control signal from the second output, and wherein the interconnect circuitry is configured to select between the received signals.
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Accused Products
Abstract
An integrated circuit with at least two LC-based phase-locked loop circuits and a high-speed serial interface circuit having multiple channels is provided. Each phase-locked loop circuit may include an oscillator having a varactor and multiple inductors. The oscillator may be configured to generate signals at different frequency ranges as determined by the inductors and the varactor. The LC-based phase-locked loop circuits may be produced such that all frequency ranges together provide the continuous coverage of an octave, thereby enabling the phase-locked loop circuits to generate a clock signal with high quality factors and desirable phase noise and jitter performance at an arbitrary frequency. Since the channels of the high-speed serial interface circuit may receive a clock signal having an arbitrary frequency, the high-speed serial interface circuit may be configured to support any communications protocol.
19 Citations
21 Claims
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1. An integrated circuit comprising:
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a first inductor-based phase-locked loop circuit having a first output, wherein the first phase-locked loop circuit generates a first control signal in a first frequency range at the first output; a second inductor-based phase-locked loop circuit having a second output, wherein the second phase-locked loop circuit generates a second control signal in a second frequency range at the second output, wherein the first and second frequency ranges partially overlap with respect to one another, and wherein the first and second inductor-based phase-locked loop circuits operate at different frequencies when the first inductor-based phase-locked loop circuit is operated at a given frequency in the first frequency range that does not overlap with the second frequency range; and interconnect circuitry coupled to the first and second outputs, wherein the interconnect circuitry receives the first control signal from the first output and receives the second control signal from the second output, and wherein the interconnect circuitry is configured to select between the received signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A high-speed serial interface circuit comprising:
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first phase-locked loop circuitry configured to generate a first clock signal within first and second frequency ranges; second phase-locked loop circuitry configured to generate a second clock signal within third and fourth frequency ranges, wherein a union of the first, second, third, and fourth frequency ranges covers a continuous frequency range, wherein the continuous frequency range comprises an upper limit and a lower limit, and wherein the upper limit is at least double in frequency compared to the lower limit; and a plurality of channels, wherein each channel is connected to one of the first and second phase-locked loop circuitries, and wherein each channel is configured to receive a selected one of the first and second clock signals. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A method for operating high-speed serial interface circuitry having a plurality of channels and first and second phase-locked loop circuits, wherein each of the first and second phase-locked loop circuits includes a plurality of inductors, the method comprising:
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with the first phase-locked loop circuit, producing first control signals in a first frequency range; with the second phase-locked loop circuit, producing second control signals in a second frequency range, wherein the first and second frequency ranges are partially overlapping with respect to one another; and receiving one of the first control signals in a subset of the plurality of channels. - View Dependent Claims (18, 19, 20, 21)
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Specification