Contact identification and tracking on a capacitance sensing array

• US 8,692,795 B1
• Filed: 08/24/2011
• Issued: 04/08/2014
• Est. Priority Date: 08/24/2010
• Status: Active Grant

• Current Assignee: Parade Technologies, Ltd.
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Hutnyk, Volodymyr, Mandziy, Vasyl, Kremin, Victor
• Primary Examiner(s): Eisen, Alexander
• Assistant Examiner(s): Chatly, Amit
• Application Number:
  US13/217,147
• Time in Patent Office: 958 Days
• Field of Search: 345173-178
• US Class Current: 345/174
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/04186 Touch location disambiguation
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Abstract

A technique for providing reliable position calculations for conductive inputs at the edges of a touch-sensitive array is disclosed. A matrix of sensors is completed using virtual sensors or nodes, allowing for a closer approximation of position of a conductive object. The matrix may be defined by a center point or sensor and a number of surrounding nodes or sensors.

Claims

1. A capacitance sensing apparatus comprising:

a first plurality of electrodes disposed along a first axis;

a second plurality of electrodes disposed along a second axis;

a capacitance sensing circuit coupled to the first and second pluralities of electrodes and configured to measure a plurality of capacitances representative of a conductive object proximate to the first and second pluralities of electrodes; and

a processor coupled to the capacitance sensing circuit and configured to calculate a position of at least one contact on the first and second pluralities of electrodes based on the measured capacitances, the processor configured to calculate a position based on at least one virtual node, wherein the at least one virtual node is generated to complete an N×

M matrix of nodes and is populated by mirroring capacitance data from a real node along a meridian, the meridian on at least one axis centered on the peak intersection.

2. The capacitance sensing apparatus of claim 1 wherein the first and second pluralities of electrodes comprise a plurality of diamond-shaped pads coupled together in a chain, and where in the first and second pluralities of electrodes substantially fill a sensing area.

3. The capacitance sensing apparatus of claim 1, wherein:

the first plurality of electrodes is disposed on a first layer and configured to substantially fill a sensing area; and

the second plurality of electrodes is disposed on a second layer and configured not to substantially fill the sensing area such that the first plurality of electrodes is visible in the spaces between the second plurality of electrodes.

4. The capacitance apparatus of claim 3 wherein each of the second plurality of electrodes comprises a plurality of traces coupled together at at least one end such that the traces are electrically equivalent.

5. The capacitance sensing apparatus of claim 1 wherein the processor is configured to define a N×

M matrix of intersections in an array of values representative of measured capacitances, the center of the N×

M matrix defined substantially by an intersection at which a peak capacitance value is detected.

6. The capacitance sensing apparatus of claim 5 wherein the virtual electrodes complete the N×

M matrix when the peak capacitance value is detected at a node at which the N×

M matrix extends beyond the array.

7. The capacitance sensing apparatus of claim 1 wherein the processor is configure to use a first plurality of intersections in a first direction from the peak capacitance value and a second plurality of intersections in a second direction from the peak capacitance value.

8. The capacitance sensing apparatus of claim 7 wherein the virtual nodes complete the first and second pluralities of intersections when the peak capacitance value is detect at an intersection too close to the edge of the array for a complete N×

M matrix to be defined.

9. The capacitance sensing apparatus of claim 1, wherein the real nodes are used twice in the position calculation based on the virtual nodes necessary to complete the N×

M matrix.

10. The capacitance sensing apparatus of claim 1 wherein the nodes are individual capacitance sensors each coupled to a different input of the capacitance sensing circuit.

11. A system comprising:

a capacitance sensing array comprising;

a first plurality of electrodes disposed along a first axis;

a second plurality of electrodes disposed along a second axis;

a capacitance sensing circuit coupled to the first and second pluralities of electrodes and configured to measure a plurality of capacitances formed at the intersections of the first and second pluralities of electrodes; and

a processor coupled to the capacitance sensing circuit and configured to calculate a position of at least one contact on the first and second pluralities of electrodes based on the measured capacitances, the processor configured to generate virtual values for intersections to complete an N×

M matrix of intersections that are not present on the array but necessary for the calculation of the position of the at least one contact, wherein the virtual values for intersections that are not present on the array are populated by mirroring real values for intersections that are present on the array along a meridian defined on at least one axis centered on a peak intersection.

12. The capacitance sensing apparatus of claim 11 wherein the first and second pluralities of electrodes comprise a plurality of diamond-shaped pads coupled together in a chain, and where in the first and second pluralities of electrodes substantially fill a sensing area.

13. The capacitance sensing apparatus of claim 11, wherein:

the first plurality of electrodes is disposed on a first layer and configured to substantially fill a sensing area; and

the second plurality of electrodes is disposed on second layer and configured to not substantially fill the sensing area such that the first plurality of electrodes is visible in the spaces between the second plurality of electrodes.

14. The capacitance sensing apparatus of claim 11 wherein the processor is configured to define a N×

M matrix of intersections in an array of values representative of measured capacitances, the center of the N×

M matrix defined substantially by an intersection at which a peak capacitance value is detected.

15. The capacitance sensing apparatus of claim 14 wherein the virtual electrodes complete the N×

M matrix when the peak capacitance value is detected at a node at which the N×

M matrix extends beyond the array.

16. A method for determining position of a capacitance sensing array comprising:

scanning the capacitance sensing array, the capacitance sensing array comprising a first plurality of electrodes disposed along a first axis and a second plurality of electrodes disposed along a second axis;

building an array of values corresponding to intersections of the first and second pluralities of electrodes;

identifying at least one peak intersection, wherein the peak intersection is characterized by a greater measured capacitance than any of the surrounding intersections;

determining if the peak intersection is in a location when a complete N×

M matrix may be generated about the peak intersection;

if an N×

M matrix may be generated, generating the N×

M matrix and calculating the position of the at least one contact on the array; and

if an N×

M matrix may not be generated,

defining a meridian on at least one axis centered on the peak intersection;

generating dummy intersections to complete the N×

M matrix;

populating the dummy intersections by mirroring capacitance values about the meridian; and

calculating the position of the at least one contact on the array.

17. The method of claim 16 wherein the N×

M matrix include the sensors on a first axis and a second axis, wherein the first and second axis are centered on the peak intersection.

18. The method of claim 16, wherein the scanning the capacitance sensing array comprises measured a mutual capacitance between each of the first and each of the second pluralities of electrodes.

19. The method of claim 16, wherein N and M are equal to the same number.

20. The method of claim 16, wherein scanning of the array comprises measuring capacitance at each intersection in turn.

21. The method of claim 16, wherein scanning the array comprises measuring capacitance at each intersection non-sequentially.

22. The method of claim 16, wherein scanning the array comprises measuring capacitance at a plurality of intersections representative of the entire array.

23. The method of claim 22, wherein the plurality of intersections representative of the entire array is less than the all the intersections of the array.