Cylindrical embedded capacitors

• US 8,693,163 B2
• Filed: 09/01/2010
• Issued: 04/08/2014
• Est. Priority Date: 09/01/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Su, An-Jhih, Hsieh, Chi-Chun, Wang, Tzu-Yu, Wu, Wei-Cheng, Hu, Hsien-Pin, Hou, Shang-Yun, Chiou, Wen-Chih, Jeng, Shin-Puu
• Primary Examiner(s): Matthews, Colleen
• Assistant Examiner(s): HARRISTON, WILLIAM A
• Application Number:
  US12/873,931
• Publication Number:
  US 20120049322A1
• Time in Patent Office: 1,315 Days
• Field of Search: 361/271, 361/278, 361/298.2, 361/298.4, 361/299.1, 361/301.2, 361/328
• US Class Current: 361/278
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/92 made by patterning layers, e.g. by etching conductive layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate.

Claims

1. A device comprising:

a substrate having a first region and a second region;

a capacitor formed in the first region of the substrate and comprising;

a first capacitor plate;

a first insulation layer encircling the first capacitor plate;

a second capacitor plate encircling the first insulation layer, wherein each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from a front surface of the substrate to a back surface of the substrate;

a second insulation layer encircling the second capacitor plate; and

a third capacitor plate encircling the second insulation layer, wherein each of the second insulation layer and the third capacitor plate extends from the front surface to the back surface of the substrate;

metal lines and vias connecting the first capacitor plate to the third capacitor plate;

a through-substrate via (TSV) formed in the second region of the substrate and extending from the front surface to the back surface of the substrate, wherein the TSV and the second capacitor plate are formed of a same conductive material comprising same elements and same percentages of the elements; and

a second isolation layer between the TSV and the substrate.

2. The device of claim 1, further comprising a first isolation layer extending from the front surface to the back surface of the substrate and encircling the capacitor.

3. The device of claim 1, wherein the capacitor has a cylindrical shape.

4. The device of claim 3, wherein the first capacitor plate forms a solid cylinder, and wherein each of the first insulation layer and the second capacitor plate forms a circular ring.

5. The device of claim 1, wherein the substrate is a semiconductor substrate, and wherein no active device is formed at the front surface or the back surface of the semiconductor substrate.

6. The device of claim 1, further comprising a metal bump electrically coupled to one of the first and the second capacitor plates.

10. The device of claim 1, wherein the substrate comprises a semiconductor material, and wherein the second isolation layer is in contact with the TSV and the substrate.

7. A device comprising:

an interposer, wherein no active device is formed in the interposer, and wherein the interposer comprises;

a silicon substrate having a first region and a second region;

a capacitor formed in the first region of the silicon substrate and extending from a front surface to a back surface of the silicon substrate, wherein the capacitor comprises;

a first capacitor plate;

a first insulation layer encircling the first capacitor plate; and

a second capacitor plate encircling the first insulation layer, wherein each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the silicon substrate;

a second insulation layer encircling the second capacitor plate; and

a third capacitor plate encircling the second insulation layer, wherein each of the second insulation layer and the third capacitor plate extends from the front surface to the back surface of the silicon substrate;

metal lines and vias connecting the first capacitor plate to the third capacitor plate; and

a first isolation layer extending from the front surface to the back surface of the silicon substrate, wherein the isolation layer is between and contacting the silicon substrate and the capacitor.

8. The device of claim 7 further comprising:

an interconnect structure overlying the front surface of the silicon substrate; and

a metal bump overlying the interconnect structure and electrically coupled to the capacitor through the interconnect structure.

9. The device of claim 7 further comprising:

a first metal bump on a front side of the silicon substrate, with the front surface being on the front side;

a second metal bump on a backside of the silicon substrate, with the back surface being on the backside; and

a through-substrate via (TSV) formed in the second region of the silicon substrate and extending from the front surface to the back surface of the silicon substrate, wherein the TSV electrically couples the first metal bump to the second metal bump.

11. A device comprising:

a substrate having a first major surface and a second major surface, wherein the substrate comprises a semiconductor material;

a capacitor having;

an inner capacitor plate extending through the substrate from the first major surface through to the second major surface;

a capacitor dielectric surrounding the inner capacitor plate and extending through the substrate from the first major surface through to the second major surface; and

an outer capacitor plate surrounding the capacitor dielectric and extending through the substrate from the first major surface through to the second major surface;

a first electrical contact on the first major surface and electrically contacting the inner capacitor plate;

a second electrical contact on the first major surface and electrically contacting the outer capacitor plate;

a first liner surrounding the outer capacitor plate and extending from the first major surface through to the second major surface;

a conductive through via extending from the first major surface through to the second major surface; and

a second liner surrounding the through via and extending from the first major surface through to the second major surface, wherein the first liner and the second liner are formed of a same dielectric material having same first elements and same percentages of the first elements, and wherein the second liner is in contact with the through via and the substrate.

12. The device of claim 11 wherein the conductive through via has a first diameter and the outer capacitor plate has a second diameter, the second diameter being larger than the first diameter.

13. The device of claim 11 wherein the capacitor dielectric is in the shape of an annulus and the outer capacitor plate is in the shape of an annulus.

14. The device of claim 11 further comprising a first solder bump formed on the first major surface and a second solder bump formed on the second major surface.

15. The device of claim 11, wherein the outer capacitor plate and the through via are formed of a same conductive material having same second elements and same percentages of the second elements.