AC coupled clock receiver with common-mode noise rejection

• US 8,693,557 B1
• Filed: 07/02/2009
• Issued: 04/08/2014
• Est. Priority Date: 07/02/2009
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Zhang, Liang Leon, Gonzalez, Alejandro F.
• Primary Examiner(s): Ahn, Sam K
• Assistant Examiner(s): Haider, Syed
• Application Number:
  US12/497,485
• Time in Patent Office: 1,741 Days
• Field of Search: 375/257, 375/259, 375/261, 375/294, 375/295, 375/316, 375/354, 327/109, 327/415, 327/547
• US Class Current: 375/259
• CPC Class Codes: H04L 25/0266 Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end

Abstract

A clock receiver includes a capacitive coupling circuit for filtering out direct-current voltages from a differential clock signal. In this way, the capacitive coupling circuit rejects common-mode noise in the differential clock signal. The clock receiver also includes a bias circuit for establishing a bias voltage in the differential clock signal and a differential amplifier for amplifying the differential clock signal. Further, the differential amplifier generate a feedback differential clock signal and provides the feedback differential clock signal to the bias circuit for further rejecting common-mode noise in the differential clock signal. The feedback differential clock signal functions as a negative feedback signal for rejecting common-mode noise in the differential clock signal and as a positive feedback signal for amplifying the differential clock signal. In some embodiments, the clock receiver includes a capacitive coupling circuit with a cut-off frequency above the frequency of the differential clock signal.

Claims

1. A clock receiver for rejecting common-mode noise in a differential clock signal, the clock receiver comprising:

a capacitive coupling circuit configured to receive an input differential clock signal and generate a filtered differential clock signal by high-pass filtering the input differential clock signal;

a bias voltage generator configured to generate a bias voltage;

a bias circuit coupled to the capacitive coupling circuit and the bias voltage generator, the bias circuit including a first resistor having a first end configured to receive a first component signal of the filtered differential clock signal and a second end configured to receive the bias voltage and a second resistor having a first end coupled to the second end of the first resistor and configured to receive the bias voltage and a second end configured to receive a second component signal of the filtered differential clock signal, the bias circuit configured to generate a biased differential clock signal based on the filtered differential clock signal, the bias voltage, and a feedback differential clock signal; and

a differential amplifier coupled to the bias circuit, the differential amplifier configured to generate an output differential clock signal by amplifying the biased differential clock signal and to generate the feedback differential clock signal based on the output differential clock signal.

2. The clock receiver of claim 1, wherein the feedback differential clock signal functions as a positive feedback signal for generating the biased differential clock signal and as a negative feedback signal for rejecting common-mode noise in the biased differential clock signal.

3. The clock receiver of claim 1, wherein the bias voltage generator comprises:

a voltage divider configured to generate the bias voltage; and

a capacitor coupled to the voltage divider and configured to maintain the bias voltage.

6. The clock receiver of claim 1, wherein the input differential clock signal has a frequency being less than a cut-off frequency of the capacitive coupling circuit.

4. A clock receiver for rejecting common-mode noise in a differential clock signal, the clock receiver comprising:

a capacitive coupling circuit configured to receive an input differential clock signal and generate a filtered differential clock signal by high-pass filtering the input differential clock signal;

a bias voltage generator configured to generate a bias voltage;

a bias circuit coupled to the capacitive coupling circuit and the bias voltage generator, the bias circuit configured to generate a biased differential clock signal based on the filtered differential clock signal, the bias voltage, and a feedback differential clock signal; and

a differential amplifier coupled to the bias circuit, the differential amplifier configured to generate an output differential clock signal by amplifying the biased differential clock signal and to generate the feedback differential clock signal based on the output differential clock signal, the differential amplifier including a first transistor configured to generate a first component signal of the output differential clock signal by amplifying and inverting a first component signal of the biased differential clock signal, a second transistor configured to generate a second component signal of the output differential clock signal by amplifying and inverting a second component signal of the biased differential clock signal, a first resistor coupled to the first transistor and configured to generate a first component signal of the feedback differential clock signal based the first component signal of the output differential clock signal for rejecting common-mode noise in the second component signal of the biased differential clock signal, and a second resistor coupled to the second transistor and configured to generate a second component signal of the feedback differential clock signal based on the second component signal of the output differential clock signal for rejecting common-mode noise in the first component signal of the biased differential clock signal.

5. The clock receiver of claim 4, wherein the first transistor and the second transistor are n-type metal-oxide-semiconductor transistors.

7. A communication system for rejecting common-mode noise in a differential clock signal, the system comprising:

a transmitter configured to transmit a source differential clock signal and a source data signal; and

a receiver coupled in communication with the transmitter and configured to receive the source differential clock signal as an input differential clock signal and to receive the source data signal as an input data signal, the receiver comprising;

a clock receiver configured to receive the input differential clock signal, generate a filtered differential clock signal by high-pass filtering the input differential clock signal, generate a bias voltage, and generate a biased differential clock signal based on the filtered differential clock signal, the bias voltage, and a feedback differential clock signal, the clock receiver further configured to generate an output differential clock signal by amplifying the biased differential clock signal and to generate the feedback differential clock signal based on the output differential clock signal wherein the clock receiver comprises a bias circuit configured to generate the biased differential clock signal, the bias circuit including a first resistor having a first end configured to receive a first component signal of the filtered differential clock signal and a second end configured to receive the bias voltage and a second resistor having a first end coupled to the second end of the first resistor and configured to receive the bias voltage and a second end configured to receive a second component signal of the filtered differential clock signal;

a data receiver configured to generate an output data signal based on the input data signal; and

a synchronizer coupled to the clock receiver and the data receiver, the synchronizer configured to generate a synchronized data signal by synchronizing the output data signal with the output differential clock signal.

8. The communication system of claim 7, wherein the feedback differential clock signal functions as a positive feedback signal for generating the biased differential clock signal and as a negative feedback signal for rejecting common-mode noise in the biased differential clock signal.

9. The communication system of claim 7, wherein the clock receiver comprises a bias voltage generator configured to generate the bias voltage, the bias voltage generator comprising:

a voltage divider configured to generate the bias voltage; and

a capacitor coupled to the voltage divider and configured to maintain the bias voltage.

10. The communication system of claim 7, wherein the clock receiver comprises a differential amplifier configured to generate the output differential clock signal and the feedback differential clock signal.

11. The communication system of claim 10, wherein the differential amplifier comprises:

a first transistor configured to generate a first component signal of the output differential clock signal by amplifying and inverting a first component signal of the biased differential clock signal;

a second transistor configured to generate a second component signal of the output differential clock signal by amplifying and inverting a second component signal of the biased differential clock signal;

a third resistor coupled to first transistor and configured to generate a first component signal of the feedback differential clock signal based the first component signal of the output differential clock signal for rejecting common-mode noise in the second component signal of the biased differential clock signal; and

a fourth resistor coupled to second transistor and configured to generate a second component signal of the feedback differential clock signal based on the second component signal of the output differential clock signal for rejecting common-mode noise in the first component signal of the biased differential clock signal.

12. The system of claim 7, wherein the input differential clock signal has a frequency being less than a cut-off frequency of the capacitive coupling circuit.

13. A method of rejecting common-mode noise in a differential clock signal, the method comprising:

receiving an input differential clock signal;

generating a filtered differential clock signal by high-pass filtering the input differential clock signal;

generating a bias voltage;

generating a biased differential clock signal based on the filtered differential clock signal, the bias voltage, and a feedback differential clock signal;

generating an output differential clock signal by combining the filtered differential clock signal with the bias voltage to establish the bias voltage as a common-mode voltage of the biased differential clock signal and by amplifying the biased differential clock signal; and

generating the feedback differential clock signal based on the output differential clock signal, the feedback differential clock signal operable as a positive feedback signal for generating the biased differential clock signal and as a negative feedback signal for rejecting common-mode noise in the biased differential clock signal.

14. The method of claim 13, wherein the biased differential clock signal comprises a first component signal and a second component signal, and generating the output differential signal comprises:

generating a first component signal of the output differential clock signal by amplifying and inverting a first component signal of the biased differential clock signal; and

generating a second component signal of the output differential clock signal by amplifying and inverting a second component signal of the biased differential clock signal.

15. The method of claim 14, wherein generating the feedback differential clock signal comprises:

generating a first component signal of the feedback differential clock signal based the first component signal of the output differential clock signal for rejecting common-mode noise in the second component signal of the biased differential clock signal; and

generating a second component signal of the feedback differential clock signal based on the second component signal of the output differential clock signal for rejecting common-mode noise in the first component signal of the biased differential clock signal.

16. The method of claim 13, wherein the input differential clock signal has a frequency being less than a cut-off frequency of the capacitive coupling circuit.

17. A clock receiver for rejecting common-mode noise in a differential clock signal, the clock receiver comprising:

a capacitive coupling circuit configured to receive an input differential clock signal and generate a filtered differential clock signal by high-pass filtering the input differential clock signal;

a bias voltage generator configured to generate a bias voltage;

a bias circuit coupled to the capacitive coupling circuit and the bias voltage generator, the bias circuit configured to generate a biased differential clock signal based on the filtered differential clock signal, the bias voltage, and a feedback differential clock signal; and

a differential amplifier coupled to the bias circuit, the differential amplifier configured to generate an output differential clock signal by amplifying the biased differential clock signal and to generate the feedback differential clock signal based on the output differential clock signal, the feedback differential clock signal operable as a positive feedback signal for generating the biased differential clock signal and as a negative feedback signal for rejecting common-mode noise in the biased differential clock signal.