Pulse signal output circuit and shift register

• US 8,693,617 B2
• Filed: 05/10/2013
• Issued: 04/08/2014
• Est. Priority Date: 03/02/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Amano, Seiko, Toyotaka, Kouhei, Miyake, Hiroyuki, Miyazaki, Aya, Shishido, Hideaki, Kusunoki, Koji
• Primary Examiner(s): Lam, Tuan T
• Application Number:
  US13/891,364
• Publication Number:
  US 20130250529A1
• Time in Patent Office: 333 Days
• Field of Search: None
• US Class Current: 377/64
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 25/03 all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H05K 7/02 Arrangements of circuit components or wiring on supporting structure

Abstract

An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.

Claims

1. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

wherein one of source and drain of the first transistor is electrically connected to one of source and drain of the second transistor,

wherein one of source and drain of the third transistor is electrically connected to a gate of the first transistor,

wherein one of source and drain of the fourth transistor is electrically connected to a gate of the first transistor,

wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor,

wherein one of source and drain of the fifth transistor is electrically connected to a gate of the second transistor,

wherein one of source and drain of the sixth transistor is electrically connected to the other of source and drain of the fifth transistor, and

wherein a ratio W/L of a channel width W to a channel length L of the fourth transistor is smaller than a ratio W/L of a channel width W to a channel length L of the first transistor.

2. The semiconductor device according to claim 1, further comprising a seventh transistor,

wherein one of source and drain of the seventh transistor is electrically connected to the gate of the second transistor.

3. A display module comprising:

the semiconductor device according to claim 1;

a pixel; and

a flexible printed circuit.

4. An electric device comprising:

a display module comprising the semiconductor device according to claim 1; and

a main body, an operation key, a speaker, an antenna, and an external connection terminal.

13. The semiconductor device according to claim 2, further comprising:

an eighth transistor;

wherein one of source and drain of the eighth transistor is electrically connected to the gate of the first transistor, and

wherein the other of source and drain of the eighth transistor is electrically connected to the one of source and drain of the third transistor.

5. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor

a sixth transistor;

wherein one of source and drain of the first transistor is electrically connected to one of source and drain of the second transistor,

wherein one of source and drain of the third transistor is electrically connected to a gate of the first transistor,

wherein one of source and drain of the fourth transistor is electrically connected to a gate of the first transistor,

wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor,

wherein one of source and drain of the fifth transistor is electrically connected to a gate of the second transistor,

wherein one of source and drain of the sixth transistor is electrically connected to the other of source and drain of the fifth transistor,

wherein a ratio W/L of a channel width W to a channel length L of the fourth transistor is smaller than a ratio W/L of a channel width W to a channel length L of the first transistor, and

wherein a ratio MI of a channel width if to a channel length L of the fourth transistor is smaller than a ratio W/L of a channel width W to a channel length L of the third transistor.

6. The semiconductor device according to claim 5, further comprising a seventh transistor,

wherein one of source and drain of the seventh transistor is electrically connected to the gate of the second transistor.

7. A display module comprising:

the semiconductor device according to claim 5;

a pixel; and

a flexible printed circuit.

8. An electric device comprising:

a display module comprising the semiconductor device according to claim 5; and

a main body, an operation key, a speaker, an antenna, and an external connection terminal.

14. The semiconductor device according to claim 6, further comprising:

an eighth transistor;

wherein one of source and drain of the eighth transistor is electrically connected to the gate of the first transistor, and

wherein the other of source and drain of the eighth transistor is electrically connected to the one of source and drain of the third transistor.

9. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

wherein one of source and drain of the first transistor is electrically connected to one of source and drain of the second transistor,

wherein one of source and drain of the third transistor is electrically connected to a gate of the first transistor,

wherein one of source and drain of the fourth transistor is electrically connected to a gate of the first transistor,

wherein a gate of the fourth transistor is electrically connected to a gate of the second transistor,

wherein one of source and drain of the filth transistor is electrically connected to a gate of the second transistor,

wherein one of source and drain of the sixth transistor is electrically connected to the other of source and drain of the fifth transistor, and

wherein a ratio W/L of a channel width W to a channel length L of the fourth transistor is smaller than a ratio W/L of a channel width W to a channel length L of the third transistor.

10. The semiconductor device according to claim 9, further comprising a seventh transistor,

wherein one of source and drain of the seventh transistor is electrically connected to the gate of the second transistor.

11. A display module comprising:

the semiconductor device according to claim 9;

a pixel; and

a flexible printed circuit.

12. An electric device comprising:

a display module comprising the semiconductor device according to claim 9; and

a main body, an operation key, a speaker, an antenna, and an external connection terminal.

15. The semiconductor device according to claim 10, further comprising:

an eighth transistor;

wherein one of source and drain of the eighth transistor is electrically connected to the gate of the first transistor, and

wherein the other of source and drain of the eighth transistor is electrically connected to the one of source and drain of the third transistor.