Feedback control of a chemical mechanical polishing device providing manipulation of removal rate profiles

• US 8,694,145 B2
• Filed: 11/08/2011
• Issued: 04/08/2014
• Est. Priority Date: 06/19/2001
• Status: Expired due to Fees

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Shanmugasundram, Arulkumar P., Schwarm, Alexander T., Prabhu, Gopalakrishna B.
• Primary Examiner(s): Ali, Mohammad
• Assistant Examiner(s): Saavedra, Emilio J
• Application Number:
  US13/292,029
• Publication Number:
  US 20120053721A1
• Time in Patent Office: 882 Days
• Field of Search: 700/121, 700/30, 700/31, 700/164, 700/175, 156/345.13, 156/345.12, 156/345.15, 156/345.22, 438/14, 438/692, 438/959
• US Class Current: 700/121
• CPC Class Codes: B24B 37/013 Devices or means for detecting lapping completion
• CPC Class Codes: B24B 37/042 operating processes therefor
• CPC Class Codes: B24B 49/03 according to the final size of the previously ground workpiece
• CPC Class Codes: B24B 49/04 involving measurement of the workpiece at the place of grinding during grinding operation
• CPC Class Codes: B24B 49/18 taking regard of the presence of dressing tools
• CPC Class Codes: G05B 19/00 Programme-control systems
• CPC Class Codes: G05B 19/19 characterised by positioning or contouring control systems, e.g. to control position from one programmed point to another or to control movement along a programmed continuous path
• CPC Class Codes: G05B 19/41865 characterised by job scheduling, process planning, material flow
• CPC Class Codes: G05B 2219/32053 Adjust work parameter as function of other cell
• CPC Class Codes: G05B 2219/32065 Synchronise set points of processes
• CPC Class Codes: G05B 2219/45031 Manufacturing semiconductor wafers
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/67253 Process monitoring, e.g. flow or thickness monitoring
• CPC Class Codes: H01L 21/67276 Production flow monitoring, e.g. for increasing throughput program-control systems per se G05B19/00, e.g. total factory control G05B19/418
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A method of controlling surface non-uniformity of a wafer in a polishing operation includes (a) providing a model for a wafer polishing that defines a plurality of regions on a wafer and identifies a wafer material removal rate in a polishing step of a polishing process for each of the regions, wherein the polishing process comprises a plurality of polishing steps, (b) polishing a wafer using a first polishing recipe based upon an incoming wafer thickness profile, (c) determining a wafer thickness profile for the post-polished wafer of step (b), and (d) calculating an updated polishing recipe based upon the wafer thickness profile of step (c) and the model of step (a) to maintain a target wafer thickness profile. The model can information about the tool state to improve the model quality. The method can be used to provide feedback to a plurality of platen stations.

Claims

1. A computer-implemented method for polishing substrates, the method comprising:

receiving, by a computing system including a processor, data relating to material removal rates for a plurality of substantially annular regions on a current wafer;

predicting, by the computing system, a material removal rate for each of the plurality of substantially annular regions using a wafer polishing model that is based on measurement of one or more previous wafers that have completed at least one step of a polishing process, wherein the wafer polishing model defines an effect of a tool state of the at least one polishing station on polishing effectiveness based on applying a scaling factor that depends on pad life and disk life;

calculating, by the computing system, a difference between the predicted material removal rates and actual material removal rates that are determined based on the received data;

updating, by the computer system, the wafer polishing model based on the calculated difference; and

adjusting, by the computing system, a processing parameter of the polishing process based on the updated wafer polishing model.

2. The computer-implemented method of claim 1, further comprising:

controlling, by the computing system, a polishing station during the polishing process.

3. The computer-implemented method of claim 1, wherein the wafer polishing model defines the plurality of substantially annular regions on the wafer and identifies a distinct material removal rate in a polishing step of the polishing process for each of the substantially annular regions, wherein the polishing process comprises a plurality of polishing steps.

4. The computer-implemented method of claim 1, wherein the wafer removal for a region j (AR′

_j) in the wafer polishing model is determined according to the equation;

AR′

_j=(c_11j·

x₁+c_12j)·

t₁(c_21j·

x₂+c_22j)·

t₂+(c_31j·

x₃+c_32j)·

t₃+(c_41j·

x₁+c_42j)·

t₄+(c_51j·

x₅+c_52j)·

t₅,

where x₁, x₂, x₃, x₄, and x₅ are the additional parameter values for polishing steps 1, 2, 3, 4, and 5, respectively;

t₁, t₂, t₃, t₄, and t₅ are the polishing times for polishing steps 1, 2, 3, 4, and 5, respectively, and c_a1j provides the contribution to wafer removal of the variable x in polishing step a in region j; and

c_a2j provides the contribution to wafer removal of polishing time in polishing step a.

5. The computer-implemented method of claim 1, wherein the scaling factor is:

(1+k_p·

t_p+k_d·

t_d+k_pd·

t_p·

t_d),

where the terms t_p and t_d refer to pad and disk life, respectively; and

the terms k_p, k_d and k_pd are empirically determined coefficients relating pad and disk life to removal rate.

6. The computer-implemented method of claim 1, wherein the wafer polishing model defines four or more substantially annular regions.

7. The computer-implemented method of claim 1, further comprising:

polishing, by a polishing station, the current wafer during a polishing step of the polishing process.

8. The computer-implemented method of claim 1, wherein the received data includes polishing time.

9. The computer-implemented method of claim 1, wherein the received data includes at least one of polishing time, polishing pad down forces and velocity, slurry flow and composition, conditioning time, conditioning disk down forces and velocity, or oscillating speeds of a conditioning disk and a wafer carrier.

10. The computer-implemented method of claim 1, wherein the polishing process includes instructions for polishing the wafer at each of at least three polishing stations.

11. The computer-implemented method of claim 10, wherein the polishing process includes instructions to process the wafer in the same manner on at least two of the plurality of polishing stations.

12. The computer-implemented method of claim 10, wherein the polishing process includes instructions to process the wafer in a different manner on at least two of the plurality of polishing stations.

13. The computer-implemented method of claim 10, further comprising:

for each of the plurality of polishing stations,

receiving, by the computer system, distinct data of the wafer processed by the polishing station,

predicting, by the computer system, distinct material removal rates using a distinct wafer polishing model associated with the processing station,

calculating a difference between the predicted material removal rates and actual material removal rates that are determined based on the distinct received data,

updating the distinct wafer polishing model based on the calculated difference, and

adjusting a processing parameter of the polishing process associated with the polishing station based on the updated distinct wafer polishing model.

14. The computer-implemented method of claim 13, wherein a separate polishing process is associated with each of the plurality of polishing stations.

15. A non-transitory computer-readable memory medium embodied with executable code that cause a processor to perform operations comprising:

receiving data relating to material removal rates for a plurality of substantially annular regions on a current wafer;

predicting a material removal rate for each of the plurality of substantially annular regions using a wafer polishing model that is based on measurement of one or more previous wafers that have completed at least one step of a polishing process, wherein the wafer polishing model defines an effect of a tool state of the at least one polishing station on polishing effectiveness based on applying a scaling factor that depends on pad life and disk life;

calculating a difference between the predicted material removal rates and actual material removal rates that are determined based on the received data;

updating the wafer polishing model based on the calculated difference; and

adjusting a processing parameter of the polishing process based on the updated wafer polishing model.

16. The non-transitory computer-readable memory medium of claim 15, wherein the wafer polishing model defines the plurality of substantially annular regions on the wafer and identifies a distinct material removal rate in a polishing step of the polishing process for each of the substantially annular regions, wherein the polishing process comprises a plurality of polishing steps.

17. The non-transitory computer-readable memory medium of claim 15, wherein the wafer removal for a region j (AR′

_j) in the wafer polishing model is determined according to the equation;

AR′

_j=(c_11j·

x₁+c_12j)·

t₁(c_21j·

x₂+c_22j)·

t₂+(c_31j·

x₃+c_32j)·

t₃+(c_41j·

x₁+c_42j)·

t₄+(c_51j·

x₅+c_52j)·

t₅,

where x₁, x₂, x₃, x₄, and x₅ are the additional parameter values for polishing steps 1, 2, 3, 4, and 5, respectively;

t₁, t₂, t₃, t₄, and t₅ are the polishing times for polishing steps 1, 2, 3, 4, and 5, respectively, and c_a1j provides the contribution to wafer removal of the variable x in polishing step a in region j; and

c_a2j provides the contribution to wafer removal of polishing time in polishing step a.

18. The non-transitory computer-readable memory medium of claim 15, wherein the scaling factor is:

(1+k_p·

t_p+k_d·

t_d+k_pd·

t_p·

t_d),

where the terms t_p and t_d refer to pad and disk life, respectively; and

the terms k_p, k_d and k_pd are empirically determined coefficients relating pad and disk life to removal rate.

19. The non-transitory computer-readable memory medium of claim 15, wherein the polishing process includes instructions for polishing the wafer at each of at least three polishing stations.

20. The non-transitory computer-readable memory medium of claim 19, wherein the executable code causes the processor to perform operations further comprising:

for each of the plurality of polishing stations,

receiving distinct data of the wafer processed by the polishing station,

predicting distinct material removal rates using a distinct wafer polishing model associated with the processing station,

calculating a difference between the predicted material removal rates and actual material removal rates that are determined based on the distinct received data,

updating the distinct wafer polishing model based on the calculated difference, and

adjusting an processing parameter of the polishing process associated with the polishing station based on the updated distinct wafer polishing model.