Built-in self-test methods, circuits and apparatus for concurrent test of RF modules with a dynamically configurable test structure

• US 8,694,276 B2
• Filed: 03/08/2011
• Issued: 04/08/2014
• Est. Priority Date: 01/20/2011
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Sontakke, Adesh Sharadrao, Mittal, Rajesh Kumar, Parekhji, Rubin A., Tripathi, Upendra Narayan
• Primary Examiner(s): Le, John H
• Application Number:
  US13/042,849
• Publication Number:
  US 20120191400A1
• Time in Patent Office: 1,127 Days
• Field of Search: 702/58, 702/117, 702/118, 702/119, 702/121, 714/718, 714/723, 714/724, 714/733, 714/729, 324/750.03
• US Class Current: 702/119
• CPC Class Codes: G01R 31/31716 Testing of input or output with loop-back
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: G01R 31/31917 Stimuli generation or application of test patterns to the device under test [DUT]

Abstract

A testable integrated circuit chip (80, 100) includes a functional circuit (80) having modules (IP.i), a storage circuit (110) operable to hold a table representing sets of compatible tests that are compatible for concurrence, and an on-chip test controller (140, 150) coupled with said storage circuit (110) and with said functional circuit modules (IP.i), said test controller (140, 150) operable to dynamically schedule and trigger the tests in those sets, whereby promoting concurrent execution of tests in said functional circuit modules (IP.i). Other circuits, wireless chips, systems, and processes of operation and processes of manufacture are disclosed.

Claims

1. A testable integrated circuit chip comprising:

a functional circuit having modules;

a storage circuit operable to hold a table representing sets of compatible tests that are compatible for concurrence; and

an on-chip test controller coupled with said storage circuit and with said functional circuit modules, said test controller operable to dynamically schedule and trigger the tests in those sets, whereby promoting concurrent execution of tests in said functional circuit modules.

2. The testable integrated circuit chip claimed in claim 1 wherein said test controller has address control logic and an address generator fed by said address control logic, said address generator coupled to supply a latest address to access said storage circuit.

3. The testable integrated circuit chip claimed in claim 1 wherein said test controller is operable to trigger at least a pair of such compatible tests to run in parallel, and then proceed to a further test operation depending on which test in the at least a pair of such compatible tests finishes first.

4. The testable integrated circuit chip claimed in claim 1 wherein said test controller is operable to trigger at least two concurrent tests and access a next set in the table if one of the concurrent tests thus triggered finishes first and to make that finished test inapplicable in such next set.

5. The testable integrated circuit chip claimed in claim 4 wherein said test controller is further operable, in case another particular test finishes first instead among the at least two concurrent tests, to allow continued execution of any remaining particular test among the at least two concurrent tests.

6. The testable integrated circuit chip claimed in claim 1 further comprising a pointer circuit operable to selectively point into the table for access to those sets, and wherein said test controller is operable to provide at least one control signal to control said pointer circuit.

7. The testable integrated circuit chip claimed in claim 1 wherein the table electronically represents a number of rows corresponding to those different sets of compatible tests and also electronically represents a number of columns corresponding to the different particular tests themselves among those sets.

8. The testable integrated circuit chip claimed in claim 1 further comprising an on-chip test interface coupled with said storage circuit and said functional circuit.

9. The testable integrated circuit chip claimed in claim 8 wherein the same test interface is re-used across said modules to provide for both test download and result-dump operations for said modules.

10. The testable integrated circuit chip claimed in claim 1 wherein said test controller is operable to cause one concurrent and dynamic test execution schedule to actually evolve on the chip out of a tree-shaped relationship of various possible sequences of test launches, defining respective possible schedules.

11. The testable integrated circuit chip claimed in claim 1 wherein said test controller includes a test list updating logic responsive to the table and further includes a scheduler circuit coupled to said test list updating logic and to said modules.

12. The testable integrated circuit chip claimed in claim 1 further comprising a test identification indexing circuit coupled said storage circuit to provide indirect accesses by said test controller.

13. The testable integrated circuit chip claimed in claim 1 further comprising a test identification indexing circuit, and an address generator controlled by said test controller and coupled to actuate said identification indexing circuit, said identification indexing circuit coupled to said storage circuit.

14. The testable integrated circuit chip claimed in claim 1 wherein said test controller is operable to trigger at least two compatible tests concurrently in at least one of the modules and to trigger at least one of the tests in at least two of the modules concurrently.

15. The testable integrated circuit chip claimed in claim 1 wherein said table is alterable.

16. The testable integrated circuit chip claimed in claim 1 wherein said test controller includes a test list updating logic coupled to said modules and to said storage circuit, and further includes a scheduler circuit coupled to said test list updating logic.