Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system

• US 8,694,735 B2
• Filed: 09/12/2012
• Issued: 04/08/2014
• Est. Priority Date: 02/05/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Larson, Douglas A., Cronin, Jeffrey J.
• Primary Examiner(s): Doan, Duc
• Application Number:
  US13/612,490
• Publication Number:
  US 20130007384A1
• Time in Patent Office: 573 Days
• Field of Search: None
• US Class Current: 711/138
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.

Claims

1. A method of managing read and write data transmission in a memory logic circuit, comprising:

enabling a write data bypass circuit of a first memory to decouple and store write data from a bidirectional bus responsive, at least in part, to receipt of a read command and transmission of the read command to a second memory further downstream on the bidirectional bus and issuance of a write command; and

restoring the write data to the bidirectional data bus with the write data bypass circuit of the first memory responsive, at least in part, to read data associated with the read command passing upstream on the bidirectional data bus.

2. The method of claim 1, wherein said enabling a write data bypass circuit comprises:

enabling the write data bypass circuit responsive, at least in part, to receipt of an active bypass control signal from a memory controller.

3. The method of claim 1, wherein said restoring the write data to the bidirectional data bus comprises:

enabling an output of a buffer; and

providing the write data from the buffer to the bidirectional data bus.

4. The method of claim 1, wherein the write data comprises a first set of write data, the method further comprising:

providing a second set of write data without any bypass.

5. The method of claim 1, wherein write data is stored in a data bypass register.

6. The method of claim 1, wherein the write command is issued by a memory controller.

7. A method, comprising:

decoupling write data associated with a first memory module from a bidirectional data bus with a data bypass circuit of a second memory module when an enable control signal has a first state;

after decoupling the write data from a bidirectional data bus with the data bypass circuit of the second memory module, storing the write data in a data bypass register of the data bypass circuit;

restoring the write data to the bidirectional data bus responsive, at least in part, to the enable control signal switching from the first state to a second state.

8. The method of claim 7, wherein the enable control signal is provided by a bypass select control logic.

9. The method of claim 7, wherein said decoupling write data associated with a first memory module from the bidirectional data bus comprises:

placing an output of a buffer in a high impedance state; and

coupling an output of the data bypass register to an input of the buffer.

10. The method of claim 7, wherein the write data is a first set of write data, the method further comprising:

providing a second set of write data without any bypass when the bypass control signal has the second state.

11. The method of claim 7, wherein the enable control signal has the first state when read data is on the bidirectional data bus.

12. The method of claim 7, wherein restoring the write data to the bidirectional data bus comprises:

coupling an output of an input buffer to an input of an output buffer.

13. A method, comprising:

receiving, with a memory module, a read command on a bidirectional data bus from an upstream device;

providing, with the memory module, the read command to a first downstream memory module;

decoupling, with the memory module, write data from the bidirectional data bus and storing the write data, wherein the write data corresponds to a write command issued to a second downstream memory module;

receiving read data corresponding to the read command from the first downstream memory module;

providing the read data to the upstream device; and

responsive to providing the read data to the upstream device, restoring the write data to the bidirectional data bus to provide the write data to the second downstream memory module.

14. The method of claim 13, wherein the first downstream memory module and the second downstream memory module are configured in a point-to-point arrangement.

15. The method of claim 13, wherein said decoupling write data from the bidirectional data bus and storing the write data comprises:

decoupling the write data from a first interface of the data bypass circuit; and

wherein said restoring the write data to the bidirectional data bus comprises;

providing the write data to a second interface of the data bypass circuit.

16. The method of claim 15, wherein said providing the write data to the second interface comprises:

enabling an output of a buffer; and

providing the write data from the buffer to the bidirectional data bus.

17. The method of claim 13, wherein storing the write data comprises storing the write data in a bypass register.

18. The method of claim 13, wherein said restoring the write data to the bidirectional data bus comprises:

switching the state of a control signal provided to a multiplexer.

19. The method of claim 13, wherein said decoupling write data from the bidirectional data bus and storing the write data comprises:

decoupling the write data from the bidirectional data bus and storing the write data responsive, at least in part, to receipt of an active bypass control signal.

20. The method of claim 13, wherein the upstream device comprises a memory controller.