AT speed TAP with dual port router and command circuit

• US 8,694,844 B2
• Filed: 07/21/2011
• Issued: 04/08/2014
• Est. Priority Date: 07/29/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US13/188,078
• Publication Number:
  US 20120102375A1
• Time in Patent Office: 992 Days
• Field of Search: 714/726, 714/727, 714/729, 714/733, 714/734
• US Class Current: 714/733
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G06F 11/26 Functional testing
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H10K 2102/00 Constructional details relating to the organic devices covered by this subclass
• CPC Class Codes: H10K 2102/103 comprising indium oxides, e.g. ITO
• CPC Class Codes: H10K 50/814 combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
• CPC Class Codes: H10K 50/816 Multilayers, e.g. transparent multilayers
• CPC Class Codes: H10K 50/844 Encapsulations
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/122 Pixel-defining structures or layers, e.g. banks
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/124 Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 71/00 Manufacture or treatment specially adapted for the organic devices covered by this subclass

Abstract

A 1149.1 TAP performs at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. In a second embodiment the at-speed operations are achieved by detecting the TAP'"'"'s Exit1DR state as a CMD signal. In a third embodiment the at-speed operations are achieved by detecting the TAP'"'"'s Exit1DR and PauseDR states. In a fourth embodiment the at-speed operations are achieved by detecting the TAP'"'"'s Exit1DR and PauseDR states and inputting these states to a Dual Port Router to control the at-speed operations of a circuit. The improvements are achieved without requiring any additional IC pins beyond the 4 required TAP pins. Devices including the TAP improvements can be operated compliantly in a daisy-chain arrangement with devices that don'"'"'t include the TAP improvements.

Claims

1. An integrated circuit comprising:

A. a TDI input lead, a TCK input lead, a TMS input lead, and a TDO output lead;

B. a test access port state machine having an input coupled to the TCK input lead, an input coupled to the TMS input lead, instruction register control outputs, a multiplexer control output, and data register control outputs;

C. an instruction register having an input coupled to the TDI input lead, inputs coupled to the instruction register control outputs, and a data register enable output;

D. a data register having an input coupled to the TDI input lead, data register control inputs, and an output;

E. a command circuit having an input coupled to the TCK input lead, an input coupled to the TMS input lead, an input coupled to the data register enable output, and data register control outputs;

F. a dual port router having inputs coupled to the data register control outputs of the state machine, inputs coupled to the data register control outputs of the command circuit, a control input coupled to the data register enable output of the instruction register, and data register control outputs coupled to the data register control inputs of the data register; and

G. multiplexer circuitry having an input coupled to the output of the instruction register, an input coupled to the output of the data register, a control input coupled to the multiplexer control output, and an output coupled to the TDO output lead.

2. The integrated circuit of claim 1 in which the state machine has states of Test Logic Reset, Run Test/Idle, SelectDR, and SelectIR.

3. The integrated circuit of claim 1 including plural data registers.