Methods, systems, and articles of manufacture for implementing electronic circuit designs with simulation awareness

• US 8,694,933 B2
• Filed: 12/30/2010
• Issued: 04/08/2014
• Est. Priority Date: 07/24/2010
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Fischer, Ed, Yanagida, Bruce, Dennison, Keith, McSherry, Michael, White, David, Gopalakrishnan, Prakash
• Primary Examiner(s): Dinh, Paul
• Application Number:
  US12/982,790
• Publication Number:
  US 20120023465A1
• Time in Patent Office: 1,195 Days
• Field of Search: 716100-103, 716106-108, 716110-115, 716/119, 716/136
• US Class Current: 716/106
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Disclosed are methods, systems, and articles of manufacture for implementing electronic designs with simulation awareness. A schematic is identified or created and simulated at the schematic level to characterize the functional behavior of the circuit or to ensure the circuit design meets the required design specifications. Physical data of a component of the design is identified, created, or updated, and the electrical parasitic associated with physical data is characterized. One or more electrical characteristics associated with the parasitic is further characterized and mapped to the simulator to re-simulate the circuit design to analyze the impact of parasitics. Some embodiments re-run the same simulation process incrementally in an interactive manner by accepting incremental design or parameter changes from the design environment.

Claims

1. A computer implemented method for implementing an electronic circuit design of an electronic circuit with simulation awareness, comprising:

using at least one processor that is to perform a process, the process comprising;

identifying, determining, or updating physical data of a component that includes at least a portion of a net in a layout of the electronic circuit design;

characterizing an electrical parasitic that is associated with the physical data of the component in the layout while the layout is being physically implemented, wherein the layout contains a partial, incomplete physical design and does not pass a layout versus schematic check;

providing the electrical parasitic to a schematic of the electronic circuit design to be simulated by a schematic simulator; and

performing a schematic simulation on the schematic using at least the electrical parasitic while the layout is being physically implemented.

2. The computer implemented method of claim 1, the process further comprising:

identifying or creating a schematic design for the electronic circuit; and

identifying or generating a netlist from the schematic design.

3. The computer implemented method of claim 2, the process further comprising:

mapping the electrical parasitic to the schematic design, wherein the schematic simulation is performed by using the electrical parasitic that is mapped to the schematic design.

4. The computer implemented method of claim 1, the process further comprising:

generating a netlist directly from a physical design of the electronic circuit without identifying or creating a schematic design of the electronic circuit.

5. The computer implemented method of claim 1, the process further comprising:

comparing a first result of the schematic simulation before the act of identifying, determining, or updating the physical data and a second result of the schematic simulation after the act of identifying, determining, or updating the physical data.

6. The computer implemented method of claim 1, the process further comprising:

improving a component parameter based at least in part upon a result of the schematic simulation.

7. The computer implemented method of claim 1, the process further comprising:

reducing the electrical parasitic to an approximate form or an alternative form.

8. The computer implemented method of claim 1, the process further comprising:

performing a sampling process on one or more transient simulation waveforms; and

providing the one or more transient simulation waveforms that are sampled to a physical electronic circuit design tool.

9. The computer implemented method of claim 1, the process further comprising:

assembling an electrical characteristic that is associated with the electrical parasitic.

10. The computer implemented method of claim 9, wherein the schematic simulation is performed at the first level using at least the electrical characteristic that is assembled.

11. The computer implemented method of claim 1, the process further comprising:

synchronizing a first data for a schematic design and a second data for a physical design of the electronic circuit.

12. The computer implemented method of claim 1, in which the physical data is part of an incomplete or a partial physical design of the electronic circuit.

13. The computer implemented method of claim 1, the process further comprising:

flattening a schematic hierarchy; and

stitching the electrical parasitic to the schematic hierarchy that is flattened.

14. The computer implemented method of claim 1, the process further comprising:

identifying a schematic hierarchy;

performing a mapping or a binder process between a schematic design and a physical design of the electronic circuit; and

stitching the electrical parasitic to the schematic hierarchy that is hierarchical.

15. The computer implemented method of claim 13, the process further comprising:

generating or modifying the schematic design with the electrical parasitic that is stitched.

16. The computer implemented method of claim 14, the process further comprising:

converting the electrical parasitic to a standard parasitic exchange format.

17. The computer implemented method of claim 1, the process further comprising:

performing schematic to simulation name mapping.

18. The computer implemented method of claim 1, wherein the act of performing the simulation at the first level using at least the electrical parasitic comprises:

performing a live streaming for a live simulation result of the simulation to a design environment; and

displaying the live simulation result in a display apparatus or storing the live simulation result.

19. The computer implemented method of claim 1, in which the partial, incomplete physical design does not pass the layout versus schematic check due to lack of one or more circuit components in the partial, incomplete physical design.

20. The computer implemented method of claim 1, in which the act of performing the schematic simulation is performed on the schematic when the schematic contains only a first net of the electronic circuit design, rather all nets in a full netlist.

21. The computer implemented method of claim 1, in which the schematic simulation is invoked and performed on the schematic after a single net has been created or modified in the schematic.

22. The computer implemented method of claim 1, the process further comprising:

identifying a first net of a set of nets that dictates a performance aspect of the electronic circuit design; and

reducing parasitics for a remainder of the set of nets to be used in the schematic simulation.

23. The computer implemented method of claim 1, the process further comprising:

assembling the electrical characteristic that is associated with the electrical parasitic, wherein

the simulation is performed at the first level using at least the electrical characteristic that is assembled.

24. The computer implemented method of claim 1, the process further comprising at least one of:

generating a netlist directly from a physical design of the electronic circuit design without identifying or creating a schematic design of the electronic circuit;

comparing a first result of the simulation before the act of identifying, determining, or updating the physical data and a second result of the simulation after the act of identifying, determining, or updating the physical data;

improving a component parameter based at least in part upon a result of the simulation; and

reducing the electrical parasitic to an approximate form or an alternative form.

25. The computer implemented method of claim 1, the process further comprising:

identifying or creating a schematic design for the electronic circuit design;

identifying or generating a netlist from the schematic design; and

mapping the electrical parasitic to the schematic design, wherein

the simulation is performed by using the electrical parasitic that is mapped to the schematic design.

26. The computer implemented method of claim 1, the process further comprising:

modifying a schematic or a layout of the electronic circuit design by using at least a result of the simulation.

27. A system for implementing an electronic circuit design of an electronic circuit with simulation awareness, comprising:

at least one processor that is at least to;

identify, determine, or update physical data of a component that includes at least a portion of a net in a layout of the electronic circuit design;

characterize an electrical parasitic that is associated with the physical data of the component in the layout while the layout is being physically implemented, wherein the layout contains a partial, incomplete physical design and does not pass a layout versus schematic check;

provide the electrical parasitic to a schematic of the electronic circuit design to be simulated by a schematic simulator at a first level; and

perform a schematic simulation on the schematic at the first level using at least the electrical parasitic while the layout is being physically implemented.

28. The system of claim 27, in which the at least one processor is further to:

identify or create a schematic design for the electronic circuit;

identify or generate a netlist from the schematic design; and

map the electrical parasitic to the schematic design, wherein the simulation is performed by using the electrical parasitic that is mapped to the schematic design.

29. The system of claim 27, in which the at least one processor is further at least to:

generate a netlist directly from a physical design of the electronic circuit without identifying or creating a schematic design of the electronic circuit;

compare a first result of the simulation before the act of identifying, determining, or updating the physical data and a second result of the simulation after the act of identifying, determining, or updating the physical data;

improve a component parameter based at least in part upon a result of the simulation;

reduce an electrical parasitic to an approximate form or an alternative form;

assemble the electrical characteristic that is associated with the electrical parasitic;

or

synchronize a first data for a schematic design and a second data for a physical design of the electronic circuit.

30. The system of claim 27, in which the at least one processor is further to:

perform a sampling process on one or more transient simulation waveforms; and

provide the one or more transient simulation waveforms that are sampled to a physical electronic circuit design tool.

31. The system of claim 27, in which the at least one processor is further at least to:

flatten a schematic hierarchy; and

stitch the electrical parasitic to the schematic hierarchy that is flattened.

32. The system of claim 27, in which the at least one processor is further at least to:

identify a schematic hierarchy;

perform a mapping or a binder process between a schematic design and a physical design of the electronic circuit; and

stitch the electrical parasitic to the schematic hierarchy that is hierarchical.

33. The system of claim 27, in which the at least one processor is further to:

synchronize a first data for a schematic design and a second data for a physical design of the electronic circuit design.

34. The system of claim 27, in which the at least one processor is further to:

capture a representation of one or more circuit elements at least by flattening a schematic hierarchy and stitching the electrical parasitic to the schematic hierarchy that is flattened.

35. The system of claim 27, in which the at least one processor is further to:

identify a schematic hierarchy;

perform a mapping or a binder process between a schematic design and a physical design of the electronic circuit; and

stitch the electrical parasitic to the schematic hierarchy that is hierarchical.

36. The system of claim 27, in which the at least one processor is further to:

identifying or determining one or more transient simulation waveforms;

perform a sampling process on the one or more transient simulation waveforms; and

provide the one or more transient simulation waveforms that are sampled to a physical electronic circuit design tool.

37. The system of claim 27, in which the at least one processor is further to:

assemble the electrical characteristic that is associated with the electrical parasitic, wherein

the simulation is performed at the first level using at least the electrical characteristic that is assembled.

38. The system of claim 27, in which the at least one processor is further to:

generate a netlist directly from a physical design of the electronic circuit design without identifying or creating a schematic design of the electronic circuit;

compare a first result of the simulation before the act of identifying, determining, or updating the physical data and a second result of the simulation after the act of identifying, determining, or updating the physical data;

improve a component parameter based at least in part upon a result of the simulation;

or

reduce the electrical parasitic to an approximate form or an alternative form.

39. The system of claim 27, in which the at least one processor is further to:

identify or create a schematic design for the electronic circuit design;

identify or generate a netlist from the schematic design; and

map the electrical parasitic to the schematic design, wherein

the simulation is performed by using the electrical parasitic that is mapped to the schematic design.

40. The system of claim 27, in which the at least one processor is further to:

modify a schematic or a layout of the electronic circuit design by using at least a result of the simulation.

41. An article of manufacture having a non-transitory computer readable storage medium comprising a sequence of instructions which, when executed by at least one processor, causes the at least one processor to execute a method for implementing an electronic circuit design of an electronic circuit with simulation awareness, the method comprising:

using the at least one processor and is programmed for performing a process, the process comprising;

identifying, determining, or updating physical data of a component that includes at least a portion of a new in a layout of the electronic circuit design;

characterizing an electrical parasitic that is associated with the physical data of the component in the layout while the layout is being physically implemented, wherein the layout contains a partial, incomplete physical design and does not pass a layout versus schematic check;

providing the electrical parasitic to a schematic of the electronic circuit design to be simulated by a schematic simulator at a first level; and

performing a schematic simulation on the schematic at the first level using at least the electrical parasitic while the layout is being physically implemented.

42. The article of manufacture of claim 41, the process further comprising:

identifying or creating a schematic design for the electronic circuit;

identifying or generating a netlist from the schematic design; and

mapping the electrical parasitic to the schematic design, wherein the simulation is performed by using the electrical parasitic that is mapped to the schematic design.

43. The article of manufacture of claim 41, the process further comprising at least one of:

generating a netlist directly from a physical design of the electronic circuit without identifying or creating a schematic design of the electronic circuit;

comparing a first result of the simulation before the act of identifying, determining, or updating the physical data and a second result of the simulation after the act of identifying, determining, or updating the physical data;

improving a component parameter based at least in part upon a result of the simulation;

reducing the electrical parasitic to an approximate form or an alternative form;

assembling the electrical characteristic that is associated with the electrical parasitic; and

synchronizing a first data for a schematic design and a second data for a physical design of the electronic circuit.

44. The article of manufacture of claim 41, the process further comprising:

performing a sampling process on one or more transient simulation waveforms; and

providing the one or more transient simulation waveforms that are sampled to a physical electronic circuit design tool.

45. The article of manufacture of claim 41, the process further comprising:

flattening a schematic hierarchy; and

stitching the electrical parasitic to the schematic hierarchy that is flattened.

46. The article of manufacture of claim 41, the process further comprising:

identifying a schematic hierarchy; and

performing a mapping or a binder process between a schematic design and a physical design of the electronic circuit; and

stitching the electrical parasitic to the schematic hierarchy that is hierarchical.

47. The article of manufacture of claim 41, the process further comprising:

synchronizing a first data for a schematic design and a second data for a physical design of the electronic circuit design.

48. The article of manufacture of claim 41, the process further comprising:

capturing a representation of one or more circuit elements at least by flattening a schematic hierarchy and stitching the electrical parasitic to the schematic hierarchy that is flattened.

49. The article of manufacture of claim 41, the process further comprising:

identifying a schematic hierarchy;

performing a mapping or a binder process between a schematic design and a physical design of the electronic circuit; and

stitching the electrical parasitic to the schematic hierarchy that is hierarchical.

50. The article of manufacture of claim 41, the process further comprising:

identifying or determining one or more transient simulation waveforms;

performing a sampling process on the one or more transient simulation waveforms; and

providing the one or more transient simulation waveforms that are sampled to a physical electronic circuit design tool.

51. The article of manufacture of claim 41, the process further comprising:

assembling the electrical characteristic that is associated with the electrical parasitic, wherein

the simulation is performed at the first level using at least the electrical characteristic that is assembled.

52. The article of manufacture of claim 41, the process further comprising at least one of:

generating a netlist directly from a physical design of the electronic circuit design without identifying or creating a schematic design of the electronic circuit;

comparing a first result of the simulation before the act of identifying, determining, or updating the physical data and a second result of the simulation after the act of identifying, determining, or updating the physical data;

improving a component parameter based at least in part upon a result of the simulation; and

reducing the electrical parasitic to an approximate form or an alternative form.

53. The article of manufacture of claim 41, the process further comprising:

identifying or creating a schematic design for the electronic circuit design;

identifying or generating a netlist from the schematic design; and

mapping the electrical parasitic to the schematic design, wherein

the simulation is performed by using the electrical parasitic that is mapped to the schematic design.

54. The article of manufacture of claim 41, the process further comprising:

modifying a schematic or a layout of the electronic circuit design by using at least a result of the simulation.