Methods, systems, and articles of manufacture for implementing electronic circuit designs with electrical awareness

• US 8,694,950 B2
• Filed: 12/30/2010
• Issued: 04/08/2014
• Est. Priority Date: 07/24/2010
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: McSherry, Michael, White, David, Fischer, Ed, Yanagida, Bruce, Gopalakrishnan, Prakash, Dennison, Keith, Shah, Akshat
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US12/982,721
• Publication Number:
  US 20120023467A1
• Time in Patent Office: 1,195 Days
• Field of Search: 716/111, 716/136
• US Class Current: 716/136
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Disclosed are a method, system, and computer program product for implementing electronic circuit designs with electrical awareness. The method or the system updates the schematic level tool(s) and physical design tool(s) with electrical parasitic data or electrical characteristic data associated with electrical parasitics so both schematic and physical design tools are aware of the electrical parasitic or characteristic data in performing their functions such as extraction based simulations. The methods or systems are also aware of EM or IR-drop constraint(s) while implementing or creating a partial layout less than a complete layout. The method or the system also provides a user interface for a design tool to provide in situ, customizable, real-time information for implementing electronic circuit designs with electrical awareness. The methods or systems also support constraint verification for electronic circuit design implementation with electrical awareness.

Claims

1. A computer implemented method for implementing an electronic circuit design with electrical awareness, comprising:

using at least one processor that is programmed for performing a process that comprises;

identifying, determining, or updating physical data of a component that is situated along a partial, incomplete net in a partial, incomplete physical design of the electronic circuit design, wherein the partial, incomplete physical design fails to pass a layout versus schematic check;

characterizing an electrical parasitic that is caused by or determined from at least a physical characteristic of the component in the physical data; and

characterizing an electrical characteristic of the electrical parasitic by performing a simulation with the electrical parasitic prior to completing the partial, incomplete physical design of the electronic circuit design.

2. The computer implemented of claim 1, the process further comprising:

ensuring correctness of the physical data or other data related to the electrical parasitic or the electrical characteristic.

3. The computer implemented method of claim 2, wherein the act of ensuring the correctness comprises:

performing an extraction based simulation.

4. The computer implemented method of claim 3, wherein the act of performing the extraction based simulation comprises:

identifying or creating a schematic design for at least a portion of the electronic circuit; and

performing a simulation on the schematic design.

5. The computer implemented method of claim 4, the process further comprising:

mapping the electrical parasitic to a schematic representation; and

providing the schematic representation to a simulator to re-perform the simulation on the schematic design.

6. The computer implemented method of claim 5, the process further comprising:

comparing a pre-physical design simulation result with a post-simulation result.

7. The computer implemented method of claim 1, wherein the act of characterizing the electrical parasitic comprises:

performing an electro-migration or an IR-drop analysis.

8. The computer implemented method of claim 7, wherein the act of characterizing the electrical characteristic comprises:

determining the electrical characteristic using at least a result of the electro-migration or the IR-drop analysis.

9. The computer implemented method of claim 7, wherein the act of ensuring the correctness comprises:

determining whether the electrical characteristic meets an electro-migration related or an IR-drop related constraint.

10. The computer implemented method of claim 1, the process further comprising:

determining a hint based at least in part upon a result of the act of ensuring the correctness of the physical data or the other data; and

displaying the hint in a user interface on a display apparatus.

11. The computer implemented method of claim 10, the process further comprising:

determining whether the adjustment causes one or more violations of one or more design rules or one or more constraints.

12. The computer implemented method of claim 1, the process further comprising:

determining an adjustment based at least in part upon a result of the act of ensuring the correctness of the physical data or the other data; and

applying the adjustment to the physical data or to the other data related to the electrical parasitic or the electrical characteristic.

13. The computer implemented method of claim 12, in which the action of applying the adjustment to the physical data is performed as a part of a placement of one or more devices or a part of a routing process.

14. The computer implemented method of claim 1, the process further comprising:

providing an in situ, customizable information in a user interface.

15. The computer implemented method of claim 14, the act of providing the in situ, customizable information comprising:

displaying a portion of a physical design in a first display portion of an user interface on a display apparatus;

receiving a manipulation of the portion of the physical design; and

determining and displaying a response to the manipulation in the first display portion.

16. The computer implemented method of claim 1, in which the partial physical design does not pass a layout versus schematic check or verification.

17. The computer implemented method of claim 1, in which the act of characterizing the electrical parasitic or the act of characterizing the electrical characteristic is performed before or at a time of completing creation of a net or modification of an existing net.

18. The computer implemented method of claim 1, the process further comprising:

verifying the electrical characteristic after completion of creation or modification of a net or a partial net and before creation or modification of a second net in the partial physical design.

19. The computer implemented method of claim 1, in which the act of characterizing the electrical parasitic or the act of characterizing the electrical characteristic is performed based at least in part upon a shape or a set of shapes on a net at a time when the net is created or completed.

20. A system for implementing an electronic circuit design with electrical awareness, comprising:

at least one processor that is at least to;

identify, determine, or update physical data of a component that is situated along a partial, incomplete net in a partial, incomplete physical design of the electronic circuit design, wherein the partial, incomplete physical design fails to pass a layout versus schematic check;

characterize an electrical parasitic that is caused by or determined from at least a physical characteristic of the component in the physical data; and

characterize an electrical characteristic of the electrical parasitic by performing a simulation with the electrical parasitic prior to completing the partial, incomplete physical design of the electronic circuit design.

21. The system of claim 20, in which the at least one processor is further at least to:

ensure correctness of the physical data or other data related to the electrical parasitic or the electrical characteristic, in which the at least one processor that is to ensure the correctness of the physical data or other data is further to;

perform an extraction based simulation, wherein the at least one processor that is to perform the extraction is further to;

identify or create a schematic design for at least a portion of the electronic circuit; and

perform a simulation on the schematic design;

map the electrical parasitic to a schematic representation; and

provide the schematic representation to a simulator to re-perform the simulation on the schematic design.

22. The system of claim 20, wherein the at one processor is further to:

determine a hint based at least in part upon a result of the act of ensuring the correctness of the physical data or the other data; and

display the hint in a user interface on a display apparatus.

23. The system of claim 20, wherein the at one processor is further to:

determine an adjustment based at least in part upon a result of the act of ensuring the correctness of the physical data or the other data; and

apply the adjustment to the physical data or to the other data related to the electrical parasitic or the electrical characteristic.

24. The system of claim 20, in which the partial physical design does not pass a layout versus schematic check or verification.

25. The system of claim 20, in which the at least one processor is to characterize the electrical parasitic or to characterize the electrical characteristic before or at a time of completing creation of a net or modification of an existing net.

26. The system of claim 20, in which the at least one processor is to characterize the electrical parasitic or to characterize the electrical characteristic based at least in part upon a shape or a set of shapes on a net at a time when the net is created or completed.

27. The system of claim 20, in which the at least one processor is to apply the adjustment to the physical data as a part of a placement of one or more devices or a part of a routing process.

28. An article of manufacture comprising a non-transitory computer readable storage medium having a sequence of instructions stored thereupon which, when executed by at least one processor, causes the at least one processor to perform a method for implementing an electronic circuit design with electrical awareness, the method comprising:

using a computer system which comprises at least one processor and is programmed for performing a process, the process comprising;

identifying, determining, or updating physical data of a component that is situated along a partial, incomplete net in a partial, incomplete physical design of the electronic circuit design, wherein the partial, incomplete physical design fails to pass a layout versus schematic check;

characterizing an electrical parasitic that is caused by or determined from at least a physical characteristic of the component in the physical data; and

characterizing an electrical characteristic of the electrical parasitic by performing a simulation with the electrical parasitic prior to completing the partial, incomplete physical design of the electronic circuit design.

29. The article of manufacture of claim 28, the process further comprising:

ensuring correctness of the physical data or other data related to the electrical parasitic or the electrical characteristic, in which the act of ensuring the correctness of the physical data or other data comprises;

performing an extraction based simulation, the act of performing the extraction comprises;

identifying or creating a schematic design for at least a portion of the electronic circuit; and

performing a simulation on the schematic design;

mapping the electrical parasitic to a schematic representation; and

providing the schematic representation to a simulator to re-perform the simulation on the schematic design.

30. The article of manufacture of claim 28, the process further comprising:

determining a hint based at least in part upon a result of the act of ensuring the correctness of the physical data or the other data; and

displaying the hint in a user interface on a display apparatus.

31. The article of manufacture of claim 28, the process further comprising:

determining an adjustment based at least in part upon a result of the act of ensuring the correctness of the physical data or the other data; and

applying the adjustment to the physical data or to the other data related to the electrical parasitic or the electrical characteristic.

32. The article of manufacture of claim 28, in which the partial physical design does not pass a layout versus schematic check or verification.

33. The article of manufacture of claim 28, in which the act of characterizing the electrical parasitic or the act of characterizing the electrical characteristic is performed before or at a time of completing creation of a net or modification of an existing net.

34. The article of manufacture of claim 28, in which the act of characterizing the electrical parasitic or the act of characterizing the electrical characteristic is performed based at least in part upon a shape or a set of shapes on a net at a time when the net is created or completed.

35. The article of manufacture of claim 28, in which the act of applying the adjustment to the physical data is performed as a part of a placement of one or more devices or a part of a routing process.