Flip chip interconnection structure

• US 8,697,490 B2
• Filed: 07/01/2011
• Issued: 04/15/2014
• Est. Priority Date: 03/10/2000
• Status: Expired due to Fees

• Current Assignee: Stats Chippac Limited
• Original Assignee: Stats Chippac Limited
• Inventors: Pendse, Rajendra D.
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): CHIU, TSZ K
• Application Number:
  US13/175,694
• Publication Number:
  US 20110260321A1
• Time in Patent Office: 1,019 Days
• Field of Search: 257/780, 257/781, 257/E21.503, 257/E21.511, 257/E23.012, 257/E23.067, 257/E23.069, 257/E23.078, 257/710, 257/704, 257/248, 257/784, 228/180.22
• US Class Current: 438/107
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1411 the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/1601 Structure
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/17107 the bump connectors connecting two common bonding areas
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81194 Lateral distribution of the bump connectors
• CPC Class Codes: H01L 2224/81345 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/81385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/838 Bonding techniques
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/53228 : the principal metal being copper
• CPC Class Codes: H01L 23/53242 : the principal metal being a noble metal, e.g. gold
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/90 : Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: H05K 3/325 : by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor adaptations of leads inserted in holes for press-fit connections H05K3/308
• CPC Class Codes: Y10T 428/24917 : including metal layer

Abstract

A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

Claims

1. A method of making a semiconductor device, comprising:

providing a semiconductor die;

forming a plurality of copper bumps including substantially linear sidewalls over a surface of the semiconductor die;

providing a substrate;

forming a plurality of interconnect pads over a surface of the substrate; and

bonding the copper bumps to a surface of the interconnect pads by plastic deformation of the copper bumps into the surface of the interconnect pads while maintaining the substantially linear sidewalls of the copper bumps for vertical separation between the semiconductor die and substrate.

2. The method of claim 1, wherein the plastic deformation of the copper bumps into the surface of the interconnect pads provides displacement of the copper bumps perpendicular to the surface of the semiconductor die while maintaining the vertical separation between the semiconductor die and substrate.

3. The method of claim 1, further including deforming the copper bumps into the surface of the interconnect pads to reduce relative movement between the semiconductor die and substrate.

4. The method of claim 1, wherein the plastic deformation occurs along a sidewall of the copper bumps.

5. The method of claim 1, further including forming a width of the interconnect pads to be less than a width of the copper bumps.

6. The method of claim 1, further including depositing an adhesive resin between the semiconductor die and substrate.

7. A method of making a semiconductor device, comprising:

providing a semiconductor die;

forming a bump including a substantially linear sidewall over a surface of the semiconductor die;

providing a substrate;

forming an interconnect pad over a surface of the substrate; and

bonding the bump to a surface of the interconnect pad by plastic deformation of the bump into the surface of the interconnect pad while maintaining the substantially linear sidewall of the bump for vertical separation between the semiconductor die and substrate.

8. The method of claim 7, wherein the plastic deformation of the bump into the surface of the interconnect pad provides displacement of the bump perpendicular to the surface of the semiconductor die while maintaining the vertical separation between the semiconductor die and substrate.

9. The method of claim 7, further including deforming the bump into the surface of the interconnect pad to reduce relative movement between the semiconductor die and substrate.

10. The method of claim 7, further including forming the bump of gold, copper, or nickel.

11. The method of claim 7, wherein the bump undergoes plastic deformation of about 25 micrometers.

12. The method of claim 7, further including forming a width of the interconnect pad to be less than a width of the bump.

13. The method of claim 7, further including depositing an adhesive resin between the semiconductor die and substrate.

14. A method of making a semiconductor device, comprising:

providing a semiconductor die;

forming a bump over the semiconductor die;

providing a substrate;

forming an interconnect pad over the substrate; and

bonding the bump to the interconnect pad by plastic deformation of the bump into the interconnect pad while maintaining vertical separation between the semiconductor die and substrate.

15. The method of claim 14, wherein the plastic deformation of the bump into the interconnect pad provides displacement of the bump perpendicular to the semiconductor die while maintaining the vertical separation between the semiconductor die and substrate.

16. The method of claim 14, further including deforming the bump into the interconnect pad to reduce relative movement between the semiconductor die and substrate.

17. The method of claim 14, wherein the plastic deformation occurs along a sidewall of the bump.

18. The method of claim 14, further including forming the bump of gold, copper, or nickel.

19. The method of claim 14, further including forming a width of the interconnect pad to be less than a width of the bump.

20. The method of claim 14, further including depositing an adhesive resin between the semiconductor die and substrate.

21. A method of making a semiconductor device, comprising:

providing a semiconductor die;

forming an interconnect structure over the semiconductor die;

providing a substrate including an interconnect pad; and

bonding the interconnect structure to the interconnect pad by plastic deformation of the interconnect structure onto the interconnect pad.

22. The method of claim 21, wherein the plastic deformation of the interconnect structure onto the interconnect pad provides displacement of the interconnect structure perpendicular to the semiconductor die while maintaining vertical separation between the semiconductor die and substrate.

23. The method of claim 21, further including deforming the interconnect structure to reduce relative movement between the semiconductor die and substrate.

24. The method of claim 21, wherein the plastic deformation occurs along a sidewall of the interconnect structure.

25. The method of claim 21, further including forming the interconnect structure of gold, copper, or nickel.

26. The method of claim 21, further including providing a width of the interconnect pad less than a width of the interconnect structure.