Systems and methods for integrated circuits comprising multiple body biasing domains

• US 8,697,512 B2
• Filed: 12/14/2010
• Issued: 04/15/2014
• Est. Priority Date: 02/02/2004
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Koniaris, Kleanthes G., Masleid, Robert Paul, Burr, James B.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US12/968,032
• Publication Number:
  US 20110086478A1
• Time in Patent Office: 1,218 Days
• Field of Search: 438/199, 438/200, 438/202
• US Class Current: 438/199
• CPC Class Codes: H03K 19/0027 in field effect transistor circuits
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.

Claims

1. A method comprising:

forming an epitaxy layer of a first conductivity type on a semiconductor substrate of the first conductivity type;

forming in the epitaxy layer a wall structure of a second conductivity type around a first region; and

forming in the epitaxy layer a bottom buried structure of the second conductivity type under the first region and connecting the bottom buried structure to the wall structure to electrically isolate the first region from a second region in the epitaxy layer, wherein the bottom buried structure is located internally with respect to the epitaxy layer and is separated by the epitaxy layer from an interface formed between the epitaxy layer and the semiconductor substrate and located under the bottom buried structure.

2. The method of claim 1 further comprising:

depositing a metal layer on a surface of the wall structure.

3. The method of claim 1, further comprising:

forming in the epitaxy layer a second wall structure of the first conductivity type around the first region and inside a perimeter of the wall structure.

4. The method of claim 3, further comprising:

depositing a metal layer on a surface of the second wall structure.

5. The method of claim 1, further comprising:

forming a first portion of a transistor of the second conductivity type in the first region; and

forming a second portion of the transistor in the wall structure.

6. The method of claim 5, further comprising:

creating a contact to the first region to receive a body biasing voltage for the transistor.

7. The method of claim 1, further comprising:

forming a transistor of the first conductivity type in the wall structure.

8. The method of claim 7 further comprising:

creating a contact to the wall structure to receive a body biasing voltage for the transistor.

9. A method comprising:

forming an epitaxy layer of a first conductivity type on a semiconductor substrate of the first conductivity type;

forming in the epitaxy layer a wall structure of a second conductivity type around a first region;

electrically isolating the first region from a second region in the epitaxy layer, wherein said electrically isolating includes;

forming in the epitaxy layer a bottom buried structure of the second conductivity type under the first region, wherein the bottom buried structure is located internally with respect to the epitaxy layer and is separated by the epitaxy layer from an interface formed between the epitaxy layer and the semiconductor substrate and located under the bottom buried structure; and

connecting the bottom buried structure to the wall structure; and

forming in the first and second regions a first plurality of transistors of the first conductivity type and a second plurality of transistors of the second conductivity type.

10. The method of claim 9, further comprising:

depositing a metal layer on a surface of the wall structure.

11. The method of claim 9, further comprising:

forming in the epitaxy layer a second wall structure of the first conductivity type around the first region and inside a perimeter of the wall structure.

12. The method of claim 11 further comprising:

depositing a metal layer on a surface of the second wall structure.

13. The method of claim 9 further comprising:

creating a first contact to the first region to receive a first body biasing voltage.

14. The method of claim 13 further comprising:

creating a second contact to the second region to receive a second body biasing voltage.

15. A method comprising:

forming an epitaxy layer of a first conductivity type on a semiconductor substrate of the first conductivity type;

forming in the epitaxy layer a first wall structure of a second conductivity type around a first region and a second wall structure of the second conductivity type around a second region; and

electrically isolating the first region from the second region, wherein said electrically isolating includes;

forming in the epitaxy layer a first bottom buried structure of the second conductivity type under the first region and a second bottom buried structure of the second conductivity type under the second region, wherein the first bottom buried structure and the second bottom buried structure are located internally with respect to the epitaxy layer, wherein the first bottom buried structure is separated by the epitaxy layer from an interface formed between the epitaxy layer and the semiconductor substrate and located under the first bottom buried structure, and wherein the second bottom buried structure is separated by the epitaxy layer from the interface formed between the epitaxy layer and the semiconductor substrate and located under the second bottom buried structure; and

connecting the first and second bottom buried structures to the first and second wall structures, respectively.

16. The method of claim 15, further comprising:

depositing a first metal layer on a surface of the first wall structure; and

depositing a second metal layer on a surface of the second wall structure.

17. The method of claim 15, further comprising:

forming in the epitaxy layer a third wall structure of the first conductivity type around the first region and inside a perimeter of the first wall structure.

18. The method of claim 17, further comprising:

depositing a metal layer on a surface of the third wall structure.

19. The method of claim 15, further comprising:

forming a first plurality of transistors of the first conductivity type and a second plurality of transistors of the second conductivity type in the first region.

20. The method of claim 15, further comprising:

creating a first contact to the first region to receive a first body biasing voltage; and

creating a second contact to the second region to receive a second body biasing voltage.