Transistor structure having a trench drain

• US 8,697,556 B2
• Filed: 06/28/2012
• Issued: 04/15/2014
• Est. Priority Date: 10/09/2008
• Status: Active Grant

• Current Assignee: Xenogenic Development Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: Estivation Properties LLC (Intellectual Ventures LLC)
• Inventors: Davies, Robert Bruce
• Primary Examiner(s): Dickey, Thomas L
• Application Number:
  US13/535,804
• Publication Number:
  US 20130034952A1
• Time in Patent Office: 656 Days
• Field of Search: 257/328, 257/341, 257/E29.03, 438/524
• US Class Current: 438/524
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength.

Claims

1. A method comprising:

forming a tub region of a transistor, wherein the tub region includes a channel region of the transistor, wherein the tub region extends to a first depth, and wherein the tub region has an opposite conductivity type as a drain region of the transistor;

forming a trench in the drain region of the transistor to a second depth, wherein the second depth is greater than the first depth;

forming a dielectric layer over at least a portion of the trench to reduce a field strength in proximity to the tub region; and

forming a pedestal over the trench.

2. The method of claim 1, wherein a region of maximum or nearly maximum field strength is located at a corner region of the trench substantially below a major surface of the transistor where the dielectric layer does not breakdown under the maximum or nearly maximum field strength.

3. The method of claim 1, further comprising:

implanting a first dopant of a same type as the drain region in proximity to a surface of the drain region and in proximity to the channel region of the transistor to support current flow out of the channel region and into the drain region; and

implanting a second dopant through a sidewall of the trench to support current flow in proximity to the trench adjacent to the sidewall of the trench.

4. The method of claim 1, further comprising etching the trench to a depth that is greater than two times the depth of the tub region.

5. The method of claim 1, further comprising providing field line edge termination for the transistor.

6. The method of claim 1, wherein said forming a pedestal over the trench comprises:

depositing one or more dielectric layers and one or more electrically-conductive layers over the trench; and

patterning the one or more dielectric layers and the one or more electrically-conductive layers.

7. The method of claim 1, further comprising forming a vertical dielectric stack adjacent to a side of the pedestal.

8. The method of claim 7, further comprising:

undercutting at least a portion of the vertical dielectric stack; and

depositing an electrically-conductive material over the pedestal, over the vertical dielectric stack, and underneath the at least a portion of the vertical dielectric stack.

9. The method of claim 1, further comprising forming a first conductive shield layer over the trench.

10. The method of claim 9, further comprising depositing one or more dielectric layers and a second conductive shield layer over the trench.

11. The method of claim 1, wherein said forming a tub region comprises implanting a dopant within an area corresponding to a source region and the channel region of the transistor.

12. A method comprising:

forming a tub region of a transistor to a first depth, wherein the tub region includes at least a portion of a channel region of the transistor;

forming a first trench in a drain region of the transistor to a second depth greater than or equal to the first depth; and

forming a second trench within a surface of the first trench such that second trench is disposed below the first trench.

13. The method of claim 12, further comprising:

implanting a first dopant of a same type as the drain region in proximity to a surface of the drain region and in proximity to the channel region of the transistor to support current flow out of the channel region and into the drain region; and

implanting a second dopant through a sidewall of the trench to support ent flow in proximity to the trench adjacent to the sidewall of the trench.

14. The method of claim 12, further comprising etching the first trench to a depth that is greater than two times the depth of the tub region.

15. The method of claim 12, wherein the second trench forms a physical boundary for the drain region and provides field line edge termination for the transistor.

16. The method of claim 12, further comprising forming a dielectric layer on a sidewall surface of the second trench.

17. The method of claim 12, wherein the transistor comprises a substrate and one of an n-type material or a p-type material formed on the substrate, and wherein said forming a second trench within a surface of the first trench comprises forming the second trench through the one of the n-type material or the p-type material and into the substrate.

18. The method of claim 12, further comprising:

forming a first conductive shield within the first trench and approximately parallel to a sidewall of the first trench; and

forming a second conductive shield proximate to the first trench, wherein the second conductive shield is at least partially disposed within a pedestal formed over the first trench.

19. The method of claim 12, wherein said forming a tub region comprises implanting a dopant within an area corresponding to a source region and the channel region of the transistor.