Process of forming an electronic device including a trench and a conductive structure therein

• US 8,697,560 B2
• Filed: 02/24/2012
• Issued: 04/15/2014
• Est. Priority Date: 02/24/2012
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Venkatraman, Prasad, Padmanabhan, Balaji
• Primary Examiner(s): Patel, Reema
• Application Number:
  US13/404,855
• Publication Number:
  US 20130221428A1
• Time in Patent Office: 781 Days
• Field of Search: 438/259, 438/589, 438/587, 438/588
• US Class Current: 438/589
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface, wherein the patterned semiconductor layer defines a first trench and a second trench that extend from the primary surface towards the substrate. The electronic device can further include a first conductive electrode and a gate electrode within the first trench. The electronic device can still further include a second conductive electrode within the second trench. The electronic device can include a source region within the patterned semiconductor layer and disposed between the first and second trenches. The electronic device can further include a body contact region within the patterned semiconductor layer and between the first and second trenches, wherein the body contact region is spaced apart from the primary surface. Processes of forming the electronic device can take advantage of forming all trenches during processing sequence.

Claims

1. A process of forming an electronic device comprising:

providing a semiconductor layer overlying a substrate, wherein the semiconductor layer has a primary surface;

patterning the semiconductor layer to define a first trench, a second trench, and a third trench that extend from the primary surface towards the substrate, wherein the first, second and third trenches are within an active region, and the third region is disposed between the first and second trenches;

forming a first conductive structure within the first trench;

forming a second conductive structure within the second trench;

forming a third conductive structure within the third trench;

forming a first insulating layer within the first trench after forming the first conductive structure;

forming a second insulating layer within the second trench after forming the second conductive layer;

forming a first gate electrode within the first trench, wherein the first insulating layer is disposed between the gate electrode and the first conductive structure; and

forming a second gate electrode within the second trench, wherein the second insulating layer is disposed between the gate electrode and the first conductive structure,

wherein in a finished electronic device, no gate electrode is disposed above the third conductive structure.

2. The process of claim 1, further comprising forming a second insulating layer within the first and second trenches before forming the first conductive structure and forming the second conductive structure.

3. The process of claim 1, wherein forming the first conductive structure and forming the second conductive structure are performed such that at least portions of forming the first conductive structure and forming the second conductive structure are formed simultaneously during a same time period.

4. The process of claim 1, wherein patterning the semiconductor layer is performed such that the first and second trenches have substantially a same depth.

5. The process of claim 1, further comprising:

forming an interlevel dielectric layer over the semiconductor layer; and

patterning the interlevel dielectric layer to form a contact opening,

forming a body contact region within the patterned semiconductor layer and between the first and second trenches, wherein the body contact region is spaced apart from the primary surface, and forming the body contact region is formed after patterning the interlevel dielectric layer.

6. The process of claim 5, further comprising:

forming a source region within the patterned semiconductor layer and between the first and second trenches before forming the interlevel dielectric layer; and

etching through the source region after patterning the interlevel dielectric layer,

wherein forming the body contact region is formed after etching through the source region.

7. The process of claim 6, further comprising forming a conductive plug within the contact opening, wherein the conductive plug electrically connects the body contact region, the source region, and the second conductive structure to one another.

8. The process of claim 1, wherein:

patterning the semiconductor layer defines additional first trenches and additional second trenches, wherein a ratio of a number of the first trenches to a number of the second trenches is approximately 1;

1; and

forming the gate electrode comprises forming additional gate electrodes within the additional first trenches, wherein no gate electrodes are formed within the additional second trenches.

9. The process of claim 8, wherein:

forming first conductive structures comprises forming additional first conductive structures within the additional first trenches before forming the additional gate electrodes; and

forming the second conductive structures comprises forming additional second conductive structures within the additional second trenches.

10. The process of claim 9, wherein each of the second trenches includes a single second conductive structure and no other electrode.

11. A process of forming an electronic device comprising:

providing a semiconductor layer overlying a substrate, wherein the semiconductor layer has a primary surface;

patterning the semiconductor layer to define a first trench that extends from the primary surface towards the substrate, wherein the first trench is disposed within an active region;

forming a first conductive structure within the first trench;

forming a first insulating layer within the first trench after forming the first conductive structure;

forming a gate electrode within the first trench, wherein the first insulating layer is disposed between the gate electrode and the first conductive structure;

patterning the semiconductor layer to define a second trench that extends from the primary surface towards the substrate, wherein patterning the semiconductor layer to define the second trench is performed after forming the gate electrode, and the second trench is disposed within the active region; and

forming a second conductive structure within the second trench.

12. The process of claim 11, further comprising:

forming an interlevel dielectric layer over the semiconductor layer; and

patterning the interlevel dielectric layer to form a contact opening,

wherein patterning the semiconductor layer to define the second trench is performed after patterning the interlevel dielectric layer.

13. The process of claim 12, further comprising forming a body region within the semiconductor layer, wherein patterning the semiconductor layer to define the second trench is performed such that the second trench extends completely through the body region.

14. The process of claim 13, further comprising:

forming an insulating layer along a bottom and a portion of the sidewall of the second trench before forming the second conductive structure;

forming a body contact region; and

forming a conductive plug within the contact opening and a portion of the second trench after forming the second conductive structure,

wherein;

the contact opening and the second trench are substantially aligned to each other; and

the conductive plug electrically connects the body contact region, the source region, and the second conductive structure to one another.

15. A process of forming an electronic device comprising:

providing a semiconductor layer overlying a substrate, wherein the semiconductor layer has a primary surface;

patterning the semiconductor layer to define a first trench and a second trench that are within an active region and extend from the primary surface towards the substrate;

forming a first insulating layer within the first trench;

forming a second insulating layer within the second trench;

forming a first conductive structure within the first trench, wherein the first insulating layer is disposed between the first conductive structure and the semiconductor layer;

forming a second conductive structure within the second trench, wherein the second insulating layer is disposed between the second conductive structure and the semiconductor layer;

forming a third insulating layer within the first trench after forming the first conductive structure;

forming a gate electrode within the first trench, wherein the third insulating layer is disposed between the gate electrode and the first conductive structure; and

forming a body contact region within the patterned semiconductor layer and between the first and second trenches, wherein the body contact region is spaced apart from the primary surface,

wherein in a finished electronic device, no gate electrode is disposed above the second conductive structure.

16. The process of claim 15, wherein the second trench includes a single second conductive structure and no other electrode.

17. The process of claim 15, wherein the second insulating layer electrically insulates the second conductive structure from the semiconductor layer.

18. The process of claim 15, wherein:

patterning the semiconductor layer defines additional first trenches and additional second trenches in the active region, wherein a ratio of a number of the first trenches to a number of the second trenches is approximately 1;

1.

19. The process of claim 18, wherein:

forming first conductive structures comprises forming additional first conductive structures within the additional first trenches; and

forming the second conductive structures comprises forming additional second conductive structures within the additional second trenches.

20. The process of claim 18, wherein:

forming the gate electrode comprises forming additional gate electrodes within the additional first trenches, wherein no gate electrodes are formed within the additional second trenches, and forming the additional gate electrodes are formed after forming the additional first conductive structures.