Power MOSFET contact metallization

• US 8,697,571 B2
• Filed: 10/17/2012
• Issued: 04/15/2014
• Est. Priority Date: 05/12/2006
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Wong, Ronald, Qi, Jason, Terrill, Kyle, Chen, Kuo-In
• Primary Examiner(s): SMITH, BRADLEY
• Application Number:
  US13/654,230
• Publication Number:
  US 20130040457A1
• Time in Patent Office: 545 Days
• Field of Search: 438/618, 438/642, 438/648
• US Class Current: 438/648
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure includes a semiconductor device formed in a substrate; an insulator adjacent to the semiconductor device; an electrical contact electrically coupled to the semiconductor device, wherein the electrical contact includes tungsten; and an electrical connector coupled to the electrical contact, wherein the electrical connector includes aluminum. A surface of the insulator and a surface of the electrical contact form a substantially even surface.

Claims

1. A method of fabricating a structure, said method comprising:

depositing a barrier layer, wherein said barrier layer is deposited over and in contact with all surfaces of an insulator except for a second surface of said insulator that is in contact with a first surface of a substrate having a semiconductor device formed therein, wherein said barrier layer is also deposited over and in contact with said substrate in a contact area between said insulator and an adjacent insulator;

depositing a first metallized layer over said barrier layer; and

etching said first metallized layer to form an electrical contact in said contact area, wherein a substantially even surface is formed by combining a surface of said barrier layer and a surface of said electrical contact, wherein said barrier layer is between and in contact with said substrate and said electrical contact, and said semiconductor device is adjacent to and underneath said insulator and entirely isolated physically from said electrical contact and from said barrier layer by said insulator, said semiconductor device electrically coupled to said electrical contact.

2. The method of claim 1 wherein said first metallized layer comprises tungsten.

3. The method of claim 1 wherein said first metallized layer is deposited using chemical vapor deposition.

4. The method of claim 1 wherein said semiconductor device comprises a power metal oxide semiconductor field effect transistor.

5. The method of claim 1 further comprising:

depositing a second metallized layer subsequent to said etching; and

etching said second metallized layer to form an electrical connector coupled to said electrical contact.

6. The method of claim 5 wherein said second metallized layer comprises aluminum.