High-voltage oxide transistor and method of manufacturing the same

• US 8,698,246 B2
• Filed: 07/12/2012
• Issued: 04/15/2014
• Est. Priority Date: 01/03/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeon, Sang-hun, Kim, Chang-jung, Song, I-hun
• Primary Examiner(s): Nguyen, Ha Tran T
• Assistant Examiner(s): VUONG, THAI T
• Application Number:
  US13/547,200
• Publication Number:
  US 20130168770A1
• Time in Patent Office: 642 Days
• Field of Search: 438/186
• US Class Current: 257/347
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A high-voltage oxide transistor includes a substrate; a channel layer disposed on the substrate; a gate electrode disposed on the substrate to correspond to the channel layer; a source contacting a first side of the channel layer; and a drain contacting a second side of the channel layer, wherein the channel layer includes a plurality of oxide layers, and none of the plurality of oxide layers include silicon. The gate electrode may be disposed on or under the channel layer. Otherwise, the gate electrodes may be disposed respectively on and under the channel layer.

Claims

1. A high-voltage oxide transistor comprising:

a substrate;

a channel layer disposed on the substrate;

a gate electrode disposed on the substrate to correspond to the channel layer;

a source contacting a first side of the channel layer; and

a drain contacting a second side of the channel layer,

wherein the channel layer includes a plurality of oxide layers, and none of the plurality of oxide layers include silicon, and

wherein the channel layer includes a first oxide layer and a second oxide layer stacked sequentially and having different mobilities and carrier densities from each other, and a layer of the first and second oxide layers having a lower mobility and a lower carrier density is adjacent to the gate electrode.

2. The high-voltage oxide transistor of claim 1, wherein the gate electrode is disposed under the channel layer.

3. The high-voltage oxide transistor of claim 2, wherein the gate electrode includes a protrusion protruding toward the channel layer.

4. The high-voltage oxide transistor of claim 2, wherein the gate electrode includes two gate electrodes that are sequentially stacked and separated from each other, and one of the two gate electrodes, which is adjacent to the channel layer, is closer to the source than the drain.

5. The high-voltage oxide transistor of claim 1, wherein the gate electrode is disposed on the channel layer.

6. The high-voltage oxide transistor of claim 1, wherein the gate electrode is an upper gate electrode disposed on the channel layer, and a lower gate electrode is disposed under the channel layer.

7. The high-voltage oxide transistor of claim 6, wherein at least one of the upper and lower gate electrodes disposed on and under the channel layer, respectively, includes a protrusion protruding toward the channel layer.

8. The high-voltage oxide transistor of claim 6, wherein at least one of the upper and lower gate electrodes formed on and under the channel layer, respectively, includes a first gate electrode and a second gate electrode that are sequentially stacked and separated from each other, and one of the first and second gate electrode that is adjacent to the channel layer is closer to the source than the drain.

9. The high-voltage oxide transistor of claim 1, wherein a distance between the gate electrode and the drain is greater than a distance between the gate electrode and the source.

10. The high-voltage oxide transistor of claim 1, wherein the channel layer further includes a third oxide layer that is stacked on the second oxide layer, and the second oxide layer has a different mobility and carrier density from the first and third oxide layers.

11. The high-voltage oxide transistor of claim 1, wherein the channel layer further includes:

additional pairs of oxide layers that are sequentially stacked, wherein each pair of oxide layers includes the first oxide layer and the second oxide layer that are sequentially stacked.

12. The high-voltage oxide transistor of claim 1, wherein the first oxide layer includes first group materials and second group materials, the first group materials including oxygen and at least two atoms selected from a group consisting of Ga, In, Zr, Zn, Sn, Al, Hf, Ta, Ti, and the second group materials including oxygen and at least two atoms selected from a group consisting of X, Zn, Sn, and Al, where X is a lanthanum-based atom.

13. The high-voltage oxide transistor of claim 1, wherein the second oxide layer includes one of an In—

Zn—

O layer, a Ga—

Zn—

O layer, and Al—

Zn—

O layer, and In—

O layer, or and In—

Sn—

O layer, and a combination thereof.

14. A method of manufacturing a high-voltage oxide transistor, the method comprising:

forming a channel layer on a substrate;

forming a source and a drain respectively contacting a first side and a second side of the channel layer; and

forming a gate electrode facing the channel layer with a gate insulating layer between the channel layer and the gate electrode,

wherein the channel layer is formed by sequentially stacking a plurality of oxide layers, and none of the plurality of oxide layers include silicon, and

wherein the channel layer is formed by sequentially stacking a first oxide layer and a second oxide layer having different mobilities and carrier densities from each other, and one having a lower mobility and a lower carrier density of the first and second oxide layers is adjacent to the gate electrode.

15. The method of claim 14, wherein the gate electrode is formed at least one of on or under the channel layer.

16. The method of claim 15, wherein the gate electrode is formed to include a protrusion protruding toward the channel layer.

17. The method of claim 15, wherein the gate electrode is formed by sequentially stacking two gate electrodes to be separated from each other, and one of the two gate electrodes, which is adjacent to the channel layer, is closer to the source than the drain.

18. The method of claim 15, wherein when the gate electrodes are formed on and under the channel layer, the gate electrodes have different structures from each other or have the same structure as each other.

19. The method of claim 18, wherein one of the gate electrodes formed on and under the channel layer is formed to have a single-layered structure, and an other is formed to have a multi-layered structure.

20. The method of claim 14, wherein the gate electrode is farther from the drain than the source.

21. The method of claim 14, wherein the channel layer is formed to further include an additional oxide layer, and a middle oxide layer among the three oxide layers has a different mobility and carrier density from those of other of the three oxide layers.

22. The method of claim 14, wherein the channel layer is formed to further stack additional pairs of oxide layers, wherein each pair of oxide layers includes the first oxide layer and the second oxide layer that are sequentially stacked.