Tunnel field effect transistor and method for manufacturing same

• US 8,698,254 B2
• Filed: 09/29/2010
• Issued: 04/15/2014
• Est. Priority Date: 09/30/2009
• Status: Active Grant

• Current Assignee: National University Corporation Hokkaido University
• Original Assignee: National University Corporation Hokkaido University
• Inventors: Tomioka, Katsuhiro, Fukui, Takashi, Tanaka, Tomotaka
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): INOUSSA, MOULOUCOULAY
• Application Number:
  US13/499,333
• Publication Number:
  US 20120187376A1
• Time in Patent Office: 1,294 Days
• Field of Search: 257/27, 257/192, 257/200, 257/E49.001, 257/E29.091, 257/E29.242, 257/E21.41, 257/E29.118, 257/136, 257/242, 257/329, 257/135, 257/E29.179, 257/327, 257/328, 257/404, 257/345, 257/268, 257/392, 257/213, 257/274, 257/348, 257/E21.461
• US Class Current: 257/392
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: C23C 16/303 Nitrides
• CPC Class Codes: C23C 16/45525 Atomic layer deposition [ALD]
• CPC Class Codes: C30B 25/005 Growth of whiskers or needles
• CPC Class Codes: C30B 25/186 being specially pre-treated by, e.g. chemical or physical means
• CPC Class Codes: C30B 29/40 AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
• CPC Class Codes: H01L 21/02373 Group 14 semiconducting materials
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/66356 Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
• CPC Class Codes: H01L 29/7391 Gated diode structures

Abstract

A tunnel field effect transistor is capable of operating at a low subthreshold and is able to be manufactured easily. The tunnel field effect transistor includes a group IV semiconductor substrate having a (111) surface and doped so as to have a first conductivity type, a group III-V compound semiconductor nanowire arranged on the (111) surface and containing a first region connected to the (111) surface and a second region doped so as to have a second conductivity type, a source electrode connected to the group IV semiconductor substrate; a drain electrode connected to the second region, and a gate electrode for applying an electric field to an interface between the (111) surface and the group III-V compound semiconductor nanowire, or an interface between the first region and the second region.

Claims

1. A tunnel field effect transistor comprising:

a group IV semiconductor substrate having a (111) surface and doped so as to have a first conductivity type;

a group III-V compound semiconductor nanowire arranged on the (111) surface of the group IV semiconductor substrate and containing a first region connected to the (111) surface of the group IV semiconductor substrate and a second region doped so as to have a second conductivity type different from the first conductivity type;

a source electrode that is not in contact with the group III-V compound semiconductor nanowire and is connected to the group IV semiconductor substrate;

a drain electrode connected to the second region of the group III-V compound semiconductor nanowire; and

a gate electrode for applying an electric field to an interface between the (111) surface of the group IV semiconductor substrate and the group III-V compound semiconductor nanowire.

2. The tunnel field effect transistor according to claim 1, wherein the group IV semiconductor is silicon or germanium,

the group III-V compound semiconductor is InAs, InP, GaAs, GaN, InSb, GaSb, AlSb, AlGaAs, InGaAs, InGaN, AlGaN, GaNAs, InAsSb, GaAsSb, InGaSb, AlInSb, InGaAlN, AlInGaP, InGaAsP, GaInAsN, InGaAlSb, InGaAsSb or AlInGaPSb, and

a longitudinal axis of the group III-V compound semiconductor nanowire is perpendicular to a (111) surface of the group IV semiconductor substrate.

3. The tunnel field effect transistor according to claim 1, further comprising a gate dielectric film arranged on a side surface of the group compound semiconductor nanowire, wherein:

the gate electrode is arranged on the gate dielectric film.

4. The tunnel field effect transistor according to claim 1, wherein an interface between the (111) surface of the group IV semiconductor substrate and the group III-V compound semiconductor nanowire has neither dislocation nor defect.

9. A switch element comprising the tunnel field effect transistor according to claim 1 or 5.

5. A tunnel field effect transistor comprising:

a group IV semiconductor substrate containing a first region having a (111) surface and a second region doped so as to have a first conductivity type;

a group III-V compound semiconductor nanowire arranged on the (111) surface of the first region of the group IV semiconductor substrate and undoped or doped so as to have a second conductivity type different from the first conductivity type;

a source electrode connected to the group III-V compound semiconductor nanowire;

a drain electrode that is not in contact with the group III-V compound semiconductor nanowire and is connected to the second region of the group IV semiconductor substrate; and

a gate electrode for applying an electric field to an interface between the group III-V compound semiconductor nanowire and the (111) surface of the group IV semiconductor substrate.

6. The tunnel field effect transistor according to claim 5, wherein the group IV semiconductor is silicon or germanium,

the group III-V compound semiconductor is InAs, InP, GaAs, GaN, InSb, GaSb, AlSb, AlGaAs, InGaAs, InGaN, AlCaN, GaNAs, InAsSb, GaAsSb, InGaSb, AlInSb, InGaAlN, AlInGaP, InGaAsP, GaInAsN, InGaAlSb, InGaAsSb or AlInGaPSb, and

a longitudinal axis of the group III-V compound semiconductor nanowire is perpendicular to the (111) surface of the first region of the group IV semiconductor substrate.

7. The tunnel field effect transistor according to claim 5, further comprising a gate dielectric film that is arranged on the surface of the group IV semiconductor substrate, wherein:

the gate electrode is arranged on the gate dielectric film.

8. The tunnel field effect transistor according to claim 5, wherein the interface between the (111) surface of the group IV semiconductor substrate and the group III-V compound semiconductor nanowire has neither dislocation nor defect.