3D integrated electronic device structure including increased thermal dissipation capabilities

• US 8,698,258 B2
• Filed: 09/30/2011
• Issued: 04/15/2014
• Est. Priority Date: 09/30/2011
• Status: Active Grant

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Nagarkar, Kaustubh Ravindra, Keimel, Christopher Fred
• Primary Examiner(s): CHU, CHRIS C
• Application Number:
  US13/249,492
• Publication Number:
  US 20130082376A1
• Time in Patent Office: 928 Days
• Field of Search: 257/E29.324, 257/E21.613, 257/698, 257/678, 257/680, 257/686, 257/704, 257/710, 257/711, 257/E23.193, 257/E23.127, 257/E21.414, 257/419, 257/613, 438/48, 438/52, 438/64, 438/455, 438/53, 359/291, 359/292, 359/298, 361/760, 361/781, 361/783
• US Class Current: 257/419
• CPC Class Codes: B81B 3/0081 Thermal properties
• CPC Class Codes: B81B 7/0077 Other packages not provided for in groups B81B7/0035 - B81B7/0074
• CPC Class Codes: B81B 7/0093 by cooling
• CPC Class Codes: B81C 1/00261 Processes for packaging MEMS devices MEMS packages B81B7/0032, packaging of smart-MEMS B81C1/0023
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/12043 Photo diode
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

A microelectronic device structure including increased thermal dissipation capabilities. The structure including a three-dimensional (3D) integrated chip assembly that is flip chip bonded to a substrate. The chip assembly including a device substrate including an active device disposed thereon. A cap layer is physically bonded to the device substrate to at least partially define a hermetic seal about the active device. The microelectronic device structure provides a plurality of heat dissipation paths therethrough to dissipate heat generated therein.

Claims

1. An apparatus comprising:

a three-dimensional (3D) integrated chip assembly, the chip assembly comprising;

a device substrate;

a MEMS relay comprising one or more heat generating elements disposed on the device substrate;

a cap layer physically bonded to the device substrate; and

a sealing ring disposed about the MEMS relay;

a hermetic seal formed about the MEMS relay, the hermetic seal at least partially defined by the device substrate, the cap layer and the sealing ring and wherein the sealing ring is not in electrical communication with the MEMS relay and the device substrate; and

a substrate, wherein the three-dimensional (3D) integrated chip assembly is flip chip bonded to the substrate,

a plurality of electrically and thermally conductive paths having a lower thermal resistance than the MEMs relay,

wherein the plurality of electrically and thermally conductive paths extend through the three-dimensional (3D) integrated chip assembly to dissipate heat generated therein and provide electrical connections to the MEMS relay.

2. The apparatus as claimed in claim 1, further comprising a heat spreader positioned proximate the three-dimensional (3D) integrated chip assembly via a thermal interface material (TIM) for facilitating dissipation of heat from the apparatus.

3. The apparatus as claimed in claim 1, wherein the cap layer further comprises a plurality of through wafer vias formed therein and a plurality of first input/output contacts disposed over a first main surface thereof and plurality of second input/output contacts disposed over a second main surface thereof, wherein the plurality of second input/output contacts are electrically connected to the plurality of first input/output contacts through the plurality of through wafer vias.

4. The apparatus as claimed in claim 3, wherein the plurality of first input/output contacts disposed over the first main surface of the cap layer facilitate coupling to a plurality of input/output pads of the substrate to which the cap layer is to be attached, and

wherein the plurality of second input/output contacts disposed over the second main surface of the cap layer facilitate coupling to a plurality of input/output contacts of the device substrate to which the cap layer is also to be attached.

5. The apparatus as claimed in claim 1, wherein the device substrate further comprises a plurality of through wafer vias formed therein and a plurality of first input/output contacts disposed over a first main surface thereof, wherein the plurality of first input/output contacts are electrically connected to the MEMS relay through the plurality of through wafer vias.

6. The apparatus as claimed in claim 5, wherein the plurality of first input/output contacts disposed over the first main surface of the device substrate facilitate coupling to a plurality of input/output pads of a substrate to which the device substrate is to be attached, and

wherein the plurality of thermally conductive traces disposed over the second main surface of the device substrate facilitate coupling of the MEMS relay to the device substrate.

7. An apparatus comprising:

a three-dimensional (3D) integrated chip assembly, the chip assembly comprising;

a device substrate including a MEMS relay comprising one or more integrated circuits disposed on the device substrate;

a cap layer comprising a semiconductor material, the cap layer physically bonded to the device substrate;

a sealing ring disposed about the MEMS relay;

a hermetic seal formed about the MEMS relay, the hermetic seal at least partially defined by the device substrate, and the cap layer and the sealing ring and wherein the sealing ring is not in electrical communication with the MEMS relay and the device substrate;

a substrate, wherein the three-dimensional (3D) integrated chip assembly is flip chip bonded to the substrate; and

a heat spreader positioned proximate the three-dimensional (3D) integrated chip assembly via a thermal interface material (TIM),

a plurality of electrically and thermally conductive paths having a lower thermal resistance than the MEMs relay, wherein the plurality of electrically and thermally conductive paths extend through the three-dimensional (3D) integrated chip assembly to dissipate heat generated within the apparatus and provide electrical connections to the MEMS relay.

8. The apparatus as claimed in claim 7, wherein the cap layer further comprises a plurality of through wafer vias formed therein and a plurality of first input/output contacts disposed over a first main surface thereof and plurality of second input/output contacts disposed over a second main surface thereof, wherein the plurality of second input/output contacts are electrically connected to the plurality of first input/output contacts through the plurality of through wafer vias, and

wherein the plurality of first input/output contacts disposed over the first main surface of the cap layer facilitate coupling to a plurality of input/output pads of the substrate to which the cap layer is to be attached, and

wherein the plurality of second input/output contacts disposed over the second main surface of the cap layer facilitate coupling to a plurality of input/output contacts of the device substrate to which the cap layer is also to be attached.

9. The apparatus as claimed in claim 7, wherein the device substrate further comprises a plurality of through wafer vias formed therein and a plurality of first input/output contacts disposed over a first main surface thereof, wherein the plurality of first input/output contacts are electrically connected to the MEMS relay through the plurality of through wafer vias and a plurality of thermally conductive traces, and wherein the plurality of first input/output contacts disposed over the first main surface of the device substrate facilitate coupling to a plurality of input/output pads of the substrate to which the device substrate is to be attached.

10. The apparatus of claim 7, wherein the substrate is one of a printed circuit board (PCB) or a flexible substrate.

11. The apparatus of claim 7, wherein the substrate is comprised of a semiconductor material and the cap layer is comprised of a semiconductor material that matches at least in part the semiconductor material of the substrate.

12. The apparatus of claim 7, wherein the device substrate is an active device layer.

13. An apparatus comprising:

a MEMS relay device including a cap layer, a device substrate, a sealing ring and a hermetic seal formed about the MEMS relay device and at least partially defined by the cap layer, the device substrate and the sealing and wherein the sealing ring is not in electrical communication with the MEMS relay device and the device substrate; and

a substrate,

wherein the MEMS relay device is configured to be flip chip bonded to the substrate.

14. The apparatus as claimed in claim 13, wherein the cap layer further comprises a plurality of through wafer vias formed therein and a plurality of first input/output contacts disposed over a first main surface thereof and plurality of second input/output contacts disposed over a second main surface thereof, wherein the plurality of second input/output contacts are electrically connected to the plurality of first input/output contacts through the plurality of through wafer vias, and

wherein the plurality of first input/output contacts disposed over the first main surface of the cap layer facilitate coupling to a plurality of input/output pads of the substrate to which the cap layer is to be attached, and

wherein the plurality of second input/output contacts disposed over the second main surface of the cap layer facilitate coupling to a plurality of input/output contacts of the device substrate to which the cap layer is also to be attached.

15. The apparatus as claimed in claim 13, wherein the device substrate further comprises a plurality of through wafer vias formed therein and a plurality of first input/output contacts disposed over a first main surface thereof, wherein the plurality of first input/output contacts are electrically connected to the MEMS relay device through the plurality of through wafer vias and a plurality of thermally conductive trace, and wherein the plurality of first input/output contacts disposed over the first main surface of the device substrate facilitate coupling to a plurality of input/output pads of the substrate to which the device substrate is to be attached.