Substrate contact opening

• US 8,698,306 B2
• Filed: 05/20/2010
• Issued: 04/15/2014
• Est. Priority Date: 05/20/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Wu, Jiun Yi
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US12/784,298
• Publication Number:
  US 20110285012A1
• Time in Patent Office: 1,426 Days
• Field of Search: None
• US Class Current: 257/737
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0381 Cleaning, e.g. oxide removal step, desmearing
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05681 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/13006 Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1403 : Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01084 : Polonium [Po]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

An under-bump metallization (UBM) structure for a substrate, such as an organic substrate, a ceramic substrate, a silicon or glass interposer, a high density interconnect, a printed circuit board, or the like, is provided. A buffer layer is formed over a contact pad on the substrate such that at least a portion of the contact pad is exposed. A conductor pad is formed within the opening and extends over at least a portion of the buffer layer. The conductor pad may have a uniform thickness and/or a non-planar surface. The substrate may be attached to another substrate and/or a die.

Claims

1. A semiconductor structure comprising:

an integrated circuit die having a first substrate;

a second substrate comprising a first contact pad, a first buffer layer over the first contact pad such that an opening in the first buffer layer exposes at least a portion of the first contact pad, and a first conductor pad in electrical contact with the first contact pad, the first conductor pad having a non-planar surface and being formed along sidewalls of the opening and extending over at least a portion of the first buffer layer; and

a conductive material interposed between the first substrate and the second substrate, the conductive material being in direct contact with the first conductor pad.

2. The semiconductor structure of claim 1, wherein the first buffer layer comprises a polymer, an epoxy, a polyimide, a solder resist, or a photo-sensitive material.

3. The semiconductor structure of claim 1, further comprising a second buffer layer interposed between the first buffer layer and the first contact pad and a second conductor pad interposed between the first conductor pad and the first contact pad, the second conductor pad extending over a top surface of the second buffer layer.

4. The semiconductor structure of claim 3, wherein the second buffer layer comprises a polymer, an epoxy, a polyimide, a solder resist, or a photo-sensitive material.

5. The semiconductor structure of claim 1, wherein a thickness of the first conductor pad is less than about 10 μ

m.

6. The semiconductor structure of claim 1, wherein the first conductor pad comprises a composite film.

7. The semiconductor structure of claim 1, wherein the first conductor pad comprises Ta, Ti, Ni, Au, Cu, Al, or an inert metal.

8. The semiconductor structure of claim 1, wherein the second substrate comprises an organic substrate, a high density interconnect, a printed circuit board, or a silicon interposer.

9. A semiconductor structure comprising:

a first substrate having a first side and a second side, at least one of the first side and the second side being formed to accept a connection to an integrated circuit die; and

a bump stress buffer layer directly on and contacting the first side of the first substrate, the bump stress buffer layer comprising a first bump buffer layer overlying a first electrical contact, the first bump buffer layer having an opening over at least a portion of the first electrical contact, the bump stress buffer layer further comprising a plurality of first bump conductor pads, the first bump conductor pads having a uniform thickness and extending over a top surface of the first bump buffer layer.

10. The semiconductor structure of claim 9, further comprising a second substrate having electrical circuitry formed thereon, the second substrate being electrically connected to the first bump conductor pads of the first substrate using conductive bumps.

11. The semiconductor structure of claim 10, further comprising an underfill material interposed between the first substrate and the second substrate.

12. The semiconductor structure of claim 9, wherein the first bump buffer layer comprises a polymer, an epoxy, a polyimide, a solder resist, or a photo-sensitive material.

13. The semiconductor structure of claim 9, further comprising a second bump buffer layer interposed between the first bump buffer layer and the first electrical contact and a second bump conductor pad interposed between the first bump conductor pad and the first electrical contact, the second bump conductor pad extending over a top surface of the second bump buffer layer.

14. The semiconductor structure of claim 13, wherein the second bump buffer layer comprises a polymer, an epoxy, a polyimide, a solder resist, or a photo-sensitive material.

15. The semiconductor structure of claim 9, wherein a thickness of the first bump conductor pad is less than about 10 μ

m.

16. A semiconductor structure comprising:

a first substrate having a first side and a second side, at least one of the first side and the second side being formed to accept a connection to an integrated circuit die; and

a bump stress buffer layer on the first side of the first substrate, the bump stress buffer layer comprising a first bump buffer layer overlying a first electrical contact, the first bump buffer layer having an opening over at least a portion of the first electrical contact, the bump stress buffer layer further comprising a plurality of first bump conductor pads, the first bump conductor pads having a uniform thickness and extending over a top surface of the first bump buffer layer and

a ball stress buffer layer on the second side of the first substrate, the ball stress buffer layer comprising a ball buffer layer overlying a second electrical contact, the ball buffer layer having an opening over at least a portion of the second electrical contact, the ball stress buffer layer further comprising a ball conductor pad, the ball conductor pad having a uniform thickness and extending over a top surface of the ball buffer layer.

17. The semiconductor structure of claim 16, wherein the first bump buffer layer comprises a polymer, an epoxy, a polyimide, a solder resist, or a photo-sensitive material.

18. The semiconductor structure of claim 16, further comprising a second bump buffer layer interposed between the first bump buffer layer and the first electrical contact and a second bump conductor pad interposed between the first bump conductor pad and the first electrical contact, the second bump conductor pad extending over a top surface of the second bump buffer layer.

19. The semiconductor structure of claim 18, wherein the second bump buffer layer comprises a polymer, an epoxy, a polyimide, a solder resist, or a photo-sensitive material.

20. The semiconductor structure of claim 16, wherein a thickness of the first bump conductor pad is less than about 10 μ

m.