Semiconductor device

• US 8,698,315 B2
• Filed: 08/28/2012
• Issued: 04/15/2014
• Est. Priority Date: 08/30/2011
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toyota Chuo Kenkyusho (Toyota Motor Corporation)
• Original Assignee: Kabushiki Kaisha Toyota Chuo Kenkyusho (Toyota Motor Corporation)
• Inventors: Nonomura, Yutaka, Akashi, Teruhisa, Funabashi, Hirofumi, Fujiyoshi, Motohiro, Omura, Yoshiteru, Hata, Yoshiyuki
• Primary Examiner(s): CHU, CHRIS C
• Application Number:
  US13/596,859
• Publication Number:
  US 20130049212A1
• Time in Patent Office: 595 Days
• Field of Search: 257/E23.07, 257/296, 257/390, 257/416, 257773-775, 438/585, 438/618, 438/666, 438/669, 438/781
• US Class Current: 257/773
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81B 2203/033 Trenches
• CPC Class Codes: B81B 2203/0392 profiles not provided for in B81B2203/0376 - B81B2203/0384
• CPC Class Codes: B81C 1/00825 Protect against mechanical threats, e.g. against shocks, or residues B81C1/00261 take precedence
• CPC Class Codes: G01C 19/5762 the sensing mass being connected to a driving mass, e.g. driving frames
• CPC Class Codes: G01C 19/5769 Manufacturing; Mounting; Housings
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/125 by capacitive pick-up
• CPC Class Codes: G01P 15/18 in two or more dimensions
• CPC Class Codes: G01P 2015/0814 for translational movement of the mass, e.g. shuttle type
• CPC Class Codes: G01P 2015/084 the mass being suspended at more than one of its sides, e.g. membrane-type suspension, so as to permit multi-axis movement of the mass

Abstract

When forming a trench of a narrow width in a thick semiconductor layer, a trench can be formed without the occurrence of semiconductor residue. In this Specification, a semiconductor device in which a trench is formed in a semiconductor layer is disclosed. In the semiconductor layer of the semiconductor device, a compensation pattern which compensates for sudden changes in the width of the trench is formed at a place at which the width of the trench changes suddenly. In the semiconductor layer of the above-described semiconductor device, since a compensation pattern is formed at a place at which the trench width changes suddenly, in the case where forming the trench using a deep RIE method, the occurrence of steep inclined portions arising from semiconductor residue can be prevented. Consequently, when forming a trench of a narrow width in a thick semiconductor layer, the occurrence of semiconductor residue can be prevented.

Claims

1. A semiconductor device, comprising a semiconductor layer having a first trench having a first width and a second trench having a second width different from the first width and connected with the first trench, wherein

a compensation pattern for gradually compensating a difference between the first width and the second width, is formed at a place of contact between the first trench and the second trench.

2. The semiconductor device according to claim 1, comprising a tip portion interposed between the first trench and the second trench, wherein the first trench contacts the second trench in the proximity of the tip portion, and the compensation pattern is formed at the tip portion.

3. The semiconductor device according to claim 2, comprising:

a support substrate;

a movable structure;

a comb-shaped fixed electrode in a fixed position relative to the support substrate, and

a comb-shaped movable electrode in a fixed position relative to the movable structure, wherein

the fixed electrode and the movable electrode are disposed to face each other, and

the tip portion is a tip portion of the fixed electrode or a tip portion of the movable electrode.

4. The semiconductor device according to claim 3, wherein a thickness of the semiconductor layer is 200 μ

m or greater, and a ratio of depth thereof to a width of the first trench or the second trench is 20 or greater.

5. The semiconductor device according to claim 2, wherein a thickness of the semiconductor layer is 200 μ

m or greater, and a ratio of depth thereof to a width of the first trench or the second trench is 20 or greater.

6. The semiconductor device according to claim 1, comprising a tip portion interposed between the first trench and the second trench, wherein the first trench contacts the second trench in the proximity of the tip portion, and the compensation pattern is formed at a place opposing the tip portion.

7. The semiconductor device according to claim 6, comprising:

a support substrate;

a movable structure;

a comb-shaped fixed electrode in a fixed position relative to the support substrate, and

a comb-shaped movable electrode in a fixed position relative to the movable structure, wherein

the fixed electrode and the movable electrode are disposed to face each other, and

the tip portion is a tip portion of the fixed electrode or a tip portion of the movable electrode.

8. The semiconductor device according to claim 7, wherein a thickness of the semiconductor layer is 200 μ

m or greater, and a ratio of depth thereof to a width of the first trench or the second trench is 20 or greater.

9. The semiconductor device according to claim 6, wherein a thickness of the semiconductor layer is 200 μ

m or greater, and a ratio of depth thereof to a width of the first trench or the second trench is 20 or greater.

10. The semiconductor device according to claim 1, wherein a thickness of the semiconductor layer is 200 μ

m or greater, and a ratio of depth thereof to a width of the first trench or the second trench is 20 or greater.