Sample and hold circuit

• US 8,698,882 B2
• Filed: 04/14/2011
• Issued: 04/15/2014
• Est. Priority Date: 04/16/2010
• Status: Expired due to Fees

• Current Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Inventors: Moore, John Kevin
• Primary Examiner(s): Rao, Andy
• Assistant Examiner(s): ELAHI, SHAN E
• Application Number:
  US13/087,036
• Publication Number:
  US 20110261177A1
• Time in Patent Office: 1,097 Days
• Field of Search: 348/65
• US Class Current: 348/65
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

A sample and hold circuit includes a plurality of capacitors, a network of switches and a control circuit. The control circuit is operable to control the network of switches so as to sample an incoming signal onto at least some of the plurality of capacitors. In such an operation, each capacitor takes a sample of the incoming signal at a different time. The sample and hold circuit outputs a signal corresponding to an average of the samples.

Claims

1. Apparatus, comprising a sample and hold circuit comprising:

a plurality of sampling capacitors coupled at first plates to a reference supply node;

a network of switches including a first plurality of switches each coupled between an input node and a respective sampling node and a second plurality of switches each coupled between one of the sampling nodes and a second plate of a respective one of the sampling capacitors; and

a control circuit for said network of switches, said control circuit operable to control said network of switches so as to sample an incoming signal at the input node onto said plurality of capacitors by sequentially activating the second plurality of switches while the first plurality of switches are simultaneously activated such that each sampling capacitor takes a sample of the incoming signal at a different time, and then simultaneously activating the second plurality of switches while the first plurality of switches are simultaneously deactivated to output a signal corresponding to an average of said samples.

2. The apparatus as claimed in claim 1 further comprising a plurality of averaging capacitors, each averaging capacitor coupled between the second plate of a respective one of the sampling capacitors and a common node at which the average of said samples is output.

3. The apparatus as claimed in claim 2 wherein a number of sampling capacitors equals a number of averaging capacitors.

4. The apparatus as claimed in claim 3 comprising a divider circuit including a first circuit portion comprising the averaging capacitors connected to the common node and a second circuit portion comprising at least one further capacitor coupled between the common node and a reference signal input node.

5. The apparatus as claimed in claim 2, further comprising a comparator having an input connected to said common node, the comparator operable to compare the average of said samples to a time varying signal.

6. The apparatus as claimed in claim 5, further comprising an image sensor comprising a pixel array, wherein said input node is configured to receive as said incoming signal an analog signal from a pixel of said pixel array, the signal having a varying level during a pixel readout period and having a noise level during a calibration period.

7. The apparatus as claimed in claim 5 wherein said comparator has a switched feedback loop, and a single input node for receiving both the average of said samples and the time varying signal.

8. The apparatus as claimed in claim 5 wherein said image sensor is a component of a mobile device.

9. The apparatus as claimed in claim 8, wherein the mobile device is selected from the group consisting of:

a mobile phone, a personal digital assistant, a digital camera.

10. The apparatus as claimed in claim 5 wherein said image sensor is a component of an optical pointing device.

11. The apparatus as claimed in claim 5 wherein said image sensor is a component of an endoscope apparatus.

12. The apparatus as claimed in claim 5 wherein said image sensor is a component of an ambient light sensor.

13. Apparatus comprising a sample and hold circuit comprising:

a plurality of sampling capacitors coupled at first plates to a reference supply node;

a network of switches including a first plurality of switches each coupled between an input node and a second plate of a respective one of the sampling capacitors and a second plurality of switches each coupled between pairs of second plates of the sampling capacitors; and

a control circuit for said network of switches, said control circuit operable to control said network of switches such that an input signal at the input node is sampled onto each of the sampling capacitors by sequentially activating the first plurality of switches while the second plurality of switches are simultaneously deactivated such that each sampling capacitor takes a sample of the input signal at a different time and then, with the input isolated by simultaneously deactivating the first plurality of switches, simultaneously activating said second plurality of switches so as to output a signal corresponding to an average of said samples.

14. The apparatus as claimed in claim 13 wherein the sampling capacitors are used for both sampling the input signal and for averaging the samples.

15. The apparatus as claimed in claim 13 wherein said second plurality of switches are operable to connect the second plates of the sampling outputs together at a common node.

16. The apparatus as claimed in claim 15, further comprising a comparator having an input connected to said common node, the comparator operable to compare the average of said samples to a time varying signal.

17. The apparatus as claimed in claim 16, further comprising an image sensor comprising a pixel array, wherein said input node is configured to receive as said input signal an analog signal from a pixel of said pixel array, the signal having a varying level during a pixel readout period and having a noise level during a calibration period.

18. The apparatus as claimed in claim 16 wherein said comparator has a switched feedback loop, and a single input node for receiving both the average of said samples and the time varying signal.

19. The apparatus as claimed in claim 16 further comprising one or more scaling capacitors coupled between said common node and the input of said comparator.

20. The apparatus as claimed in claim 17 wherein said image sensor is a component of a mobile device.

21. The apparatus as claimed in claim 20, wherein the mobile device is selected from the group consisting of:

a mobile phone, a personal digital assistant, a digital camera.

22. The apparatus as claimed in claim 17 wherein said image sensor is a component of an optical pointing device.

23. The apparatus as claimed in claim 17 wherein said image sensor is a component of an endoscope apparatus.

24. The apparatus as claimed in claim 17 wherein said image sensor is a component of an ambient light sensor.

25. Apparatus comprising:

a first sampling circuit, comprising;

a first plurality of first sampling capacitors coupled at first plates to a first signal node configured to receive a ramp signal;

a first network of switches including a first plurality of switches each coupled between a first input node and a second plate of a respective one of the first sampling capacitors and a second plurality of switches each coupled between pairs of second plates of the first sampling capacitors;

a second sampling circuit, comprising;

a second plurality of second sampling capacitors coupled at first plates to a second signal node configured to receive a ramp offset signal;

a second network of switches including a third plurality of switches each coupled between a second input node and a second plate of a respective one of the second sampling capacitors and a second plurality of switches each coupled between pairs of second plates of the second sampling capacitors;

a comparator having a first input coupled to an output of the first sampling circuit and a second input coupled to an output of the second sampling circuit; and

a control circuit for said first and second networks of switches, said control circuit operable to control said first and second networks of switches such that input signals at the first and second input nodes are sampled onto each of the first and second sampling capacitors, respectively, by sequentially activating the first and third plurality of switches while the second and fourth plurality of switches are simultaneously deactivated such that each first and second sampling capacitor takes a sample at a different time and then, with the first and second input nodes isolated by simultaneously deactivating the first and third plurality of switches, simultaneously activating said second and fourth plurality of switches so as to output to the first input of the comparator a first signal corresponding to an average of said samples of the first input signal and output to the second input of the comparator a second signal corresponding to an average of said samples of the second input signal.

26. The apparatus of claim 25 wherein the first input signal is an active pixel signal and the second input signal is a black pixel signal.