Three-dimensional writable printed memory

• US 8,699,257 B2
• Filed: 08/30/2012
• Issued: 04/15/2014
• Est. Priority Date: 09/01/2011
• Status: Expired due to Fees

• Current Assignee: Guobiao Zhang, Hangzhou Haicun Information Technology Co., Ltd.
• Original Assignee: Guobiao Zhang, Hangzhou Haicun Information Technology Co., Ltd.
• Inventors: Zhang, Guobiao
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US13/599,112
• Publication Number:
  US 20130058147A1
• Time in Patent Office: 593 Days
• Field of Search: 365/105
• US Class Current: 365/105
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/10 in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 17/143 using laser-fusible links
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence

Abstract

The present invention discloses a three-dimensional writable printed memory (3D-wP). It comprises at least a printed memory array and a writable memory array. The printed memory array stores contents data, which are recorded with a printing means; the writable memory array stores custom data, which are recorded with a writing means. The writing means is preferably direct-write lithography. To maintain manufacturing throughput, the total amount of custom data should be less than 1% of the total amount of content data.

Claims

1. A three-dimensional writable printed memory (3D-wP), comprising:

a semiconductor substrate;

a plurality of vertically stacked memory levels stacked above and coupled to said substrate, said memory levels comprising a plurality of printed memory arrays whose patterns represent content data;

at least a writable memory array whose patterns represent custom data;

wherein the total amount of said custom data is less than 1% of the total amount of said content data.

2. The 3D-wP according to claim 1, wherein said content data are the same for all memory devices in a same batch with said 3D-wP.

3. The 3D-wP according to claim 2, wherein at least two memory device in said batch have different custom data.

4. The 3D-wP according to claim 1, wherein at least a portion of said writable memory array is located below the topmost one of said memory levels.

5. The 3D-wP according to claim 4, wherein said writable memory array is located in selected one of said memory levels.

6. The 3D-wP according to claim 4, wherein said writable memory array is located below all of said memory levels.

7. The 3D-wP according to claim 1, wherein the minimum feature size of the data-coding layer for said writable memory array is larger than the minimum feature size of the data-coding layer for said printed memory arrays.

8. The 3D-wP according to claim 1, further comprising an encrypting means.

9. The 3D-wP according to claim 8, wherein said writable memory array stores at least a key for said encrypting means.

10. The 3D-wP according to claim 8, wherein said writable memory array stores chip ID.

11. The 3D-wP according to claim 8, wherein said writable memory array stores the information related to the data-array sequence.