Systems and methods for improving error distributions in multi-level cell memory systems

• US 8,699,269 B1
• Filed: 07/26/2013
• Issued: 04/15/2014
• Est. Priority Date: 03/10/2008
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Yang, Xueshi
• Primary Examiner(s): HIDALGO, FERNANDO N
• Application Number:
  US13/951,766
• Time in Patent Office: 263 Days
• Field of Search: 365/185.03, 365/185.18, 365/185.04, 365/185.09, 365/185.12, 365/185.17, 365/185.23, 365/189.011, 365/189.14, 365/230.04, 365/230.06
• US Class Current: 365/185.03
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A state set module arranges states of a memory cell in a first and a second sequence in a first and a second state set, respectively. The memory cell stores first and second bits when programmed to a state. When the states in the first and second state sets are accessed respectively in the first and the second sequence, the first and second bits of the states in the first and second state sets exhibit different number of logical transitions. A write module receives first and second sets of bits to be written as the first and second bits in a plurality of memory cells, and selects states from the first and second state sets in an alternating pattern to write the first and second sets of bits as the first and second bits in the plurality of memory cells.

Claims

1. A system comprising:

a state set module configured to

arrange a plurality of states of a memory cell (i) in a first sequence in a first state set and (ii) in a second sequence in a second state set,

wherein the memory cell is configured to store (i) a first bit and (ii) a second bit in response to being programmed to one of the plurality of states, and

wherein in response to accessing the plurality of states in the first state set and the second state set respectively in the first sequence and the second sequence, (i) the first bits of the plurality of states in the first state set and (ii) the second bits of the plurality of states in the second state set exhibit a different number of logical transitions than (i) the first bits of the plurality of states in the second state set and (ii) the second bits of the plurality of states in the first state set; and

a write module configured to

receive (i) a first set of bits to be written as the first bits in a plurality of memory cells and (ii) a second set of bits to be written as the second bits in the plurality of memory cells, and

select states from (i) the first state set and (ii) the second state in an alternating pattern to write (i) the first set of bits as the first bits in the plurality of memory cells and (ii) the second set of bits as the second bits in the plurality of memory cells.

2. The system of claim 1, further comprising an error correcting code module configured to generate (i) the first set of bits and (ii) the second set of bits based on an error-correcting code.

3. The system of claim 1, further comprising:

a memory map module configured to store the alternating pattern used to select the states from the first state set and the second state set are selected to write data to the plurality memory cells; and

a read module configured to read the data from the plurality of memory cells in accordance with the alternating pattern.

4. The system of claim 1, wherein the first bits and the second bits of the plurality of memory cells are respectively arranged along a first page and a second page, and wherein an error distribution between the first page and the second page is even.

5. The system of claim 1, wherein the plurality of memory cells includes NAND flash memory cells or NOR flash memory cells.

6. A flash memory comprising the system of claim 1.

7. The flash memory of claim 6, wherein the flash memory comprises a NAND flash memory or a NOR flash memory.

8. A method comprising:

arranging a plurality of states of a memory cell (i) in a first sequence in a first state set and (ii) in a second sequence in a second state set,

wherein the memory cell is configured to store (i) a first bit and (ii) a second bit in response to being programmed to one of the plurality of states, and

wherein in response to accessing the plurality of states in the first state set and the second state set respectively in the first sequence and the second sequence, (i) the first bits of the plurality of states in the first state set and (ii) the second bits of the plurality of states in the second state set exhibit a different number of logical transitions than (i) the first bits of the plurality of states in the second state set and (ii) the second bits of the plurality of states in the first state set;

receiving (i) a first set of bits to be written as the first bits in a plurality of memory cells and (ii) a second set of bits to be written as the second bits in the plurality of memory cells; and

selecting states from (i) the first state set and (ii) the second state in an alternating pattern to write (i) the first set of bits as the first bits in the plurality of memory cells and (ii) the second set of bits as the second bits in the plurality of memory cells.

9. The method of claim 8, further comprising generating (i) the first set of bits and (ii) the second set of bits based on an error-correcting code.

10. The method of claim 8, further comprising:

storing the alternating pattern used to select the states from the first state set and the second state set are selected to write data to the plurality memory cells; and

reading the data from the plurality of memory cells in accordance with the alternating pattern.

11. The method of claim 8, wherein the first bits and the second bits of the plurality of memory cells are respectively arranged along a first page and a second page, and wherein an error distribution between the first page and the second page is even.

12. The method of claim 8, wherein the plurality of memory cells includes NAND flash memory cells or NOR flash memory cells.