Systems and methods for improving error distributions in multi-level cell memory systems
First Claim
1. A system comprising:
- a state set module configured toarrange a plurality of states of a memory cell (i) in a first sequence in a first state set and (ii) in a second sequence in a second state set,wherein the memory cell is configured to store (i) a first bit and (ii) a second bit in response to being programmed to one of the plurality of states, andwherein in response to accessing the plurality of states in the first state set and the second state set respectively in the first sequence and the second sequence, (i) the first bits of the plurality of states in the first state set and (ii) the second bits of the plurality of states in the second state set exhibit a different number of logical transitions than (i) the first bits of the plurality of states in the second state set and (ii) the second bits of the plurality of states in the first state set; and
a write module configured toreceive (i) a first set of bits to be written as the first bits in a plurality of memory cells and (ii) a second set of bits to be written as the second bits in the plurality of memory cells, andselect states from (i) the first state set and (ii) the second state in an alternating pattern to write (i) the first set of bits as the first bits in the plurality of memory cells and (ii) the second set of bits as the second bits in the plurality of memory cells.
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Accused Products
Abstract
A state set module arranges states of a memory cell in a first and a second sequence in a first and a second state set, respectively. The memory cell stores first and second bits when programmed to a state. When the states in the first and second state sets are accessed respectively in the first and the second sequence, the first and second bits of the states in the first and second state sets exhibit different number of logical transitions. A write module receives first and second sets of bits to be written as the first and second bits in a plurality of memory cells, and selects states from the first and second state sets in an alternating pattern to write the first and second sets of bits as the first and second bits in the plurality of memory cells.
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Citations
12 Claims
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1. A system comprising:
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a state set module configured to arrange a plurality of states of a memory cell (i) in a first sequence in a first state set and (ii) in a second sequence in a second state set, wherein the memory cell is configured to store (i) a first bit and (ii) a second bit in response to being programmed to one of the plurality of states, and wherein in response to accessing the plurality of states in the first state set and the second state set respectively in the first sequence and the second sequence, (i) the first bits of the plurality of states in the first state set and (ii) the second bits of the plurality of states in the second state set exhibit a different number of logical transitions than (i) the first bits of the plurality of states in the second state set and (ii) the second bits of the plurality of states in the first state set; and a write module configured to receive (i) a first set of bits to be written as the first bits in a plurality of memory cells and (ii) a second set of bits to be written as the second bits in the plurality of memory cells, and select states from (i) the first state set and (ii) the second state in an alternating pattern to write (i) the first set of bits as the first bits in the plurality of memory cells and (ii) the second set of bits as the second bits in the plurality of memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method comprising:
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arranging a plurality of states of a memory cell (i) in a first sequence in a first state set and (ii) in a second sequence in a second state set, wherein the memory cell is configured to store (i) a first bit and (ii) a second bit in response to being programmed to one of the plurality of states, and wherein in response to accessing the plurality of states in the first state set and the second state set respectively in the first sequence and the second sequence, (i) the first bits of the plurality of states in the first state set and (ii) the second bits of the plurality of states in the second state set exhibit a different number of logical transitions than (i) the first bits of the plurality of states in the second state set and (ii) the second bits of the plurality of states in the first state set; receiving (i) a first set of bits to be written as the first bits in a plurality of memory cells and (ii) a second set of bits to be written as the second bits in the plurality of memory cells; and selecting states from (i) the first state set and (ii) the second state in an alternating pattern to write (i) the first set of bits as the first bits in the plurality of memory cells and (ii) the second set of bits as the second bits in the plurality of memory cells. - View Dependent Claims (9, 10, 11, 12)
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Specification