Semiconductor memory device
First Claim
Patent Images
1. A semiconductor memory device comprising:
- a plurality of memory cells including current paths coupled in series, and each including a charge accumulation layer and a control gate, the plurality of memory cells being stacked above a semiconductor substrate;
a plurality of word lines coupled to the control gates;
a driver circuit configured to repeat a programming operation to write data in a memory cell coupled to a selected word line, wherein a first voltage is applied to the selected word line, a second voltage is applied to a first unselected word line, and a third voltage is applied to a second unselected word line, in the programming operation; and
a control circuit configured to step up the first voltage and step down the second voltage in repeating the programming operation;
wherein the first unselected word line is adjacent to the selected word line.
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Abstract
According to one embodiment, a semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The memory cells are stacked above a semiconductor substrate, and each includes a charge accumulation layer and control gate. The word lines are coupled to the control gates. The driver circuit repeats a programming operation to write data in a memory cell coupled to a selected word line. In the programming operation, a first voltage is applied to the selected word line, a second voltage to a first unselected word line, and a third voltage to a second unselected word line. The control circuit steps up the first voltage and steps down the second voltage in repeating the programming.
9 Citations
18 Claims
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1. A semiconductor memory device comprising:
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a plurality of memory cells including current paths coupled in series, and each including a charge accumulation layer and a control gate, the plurality of memory cells being stacked above a semiconductor substrate; a plurality of word lines coupled to the control gates; a driver circuit configured to repeat a programming operation to write data in a memory cell coupled to a selected word line, wherein a first voltage is applied to the selected word line, a second voltage is applied to a first unselected word line, and a third voltage is applied to a second unselected word line, in the programming operation; and a control circuit configured to step up the first voltage and step down the second voltage in repeating the programming operation; wherein the first unselected word line is adjacent to the selected word line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A data write method of a semiconductor memory device including a plurality of memory cells including current paths coupled in series, and stacked above a semiconductor substrate, comprising:
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programming data in a selected memory cell by applying a first voltage to a gate of the selected memory cell, a second voltage to a gate of a first unselected memory cell, and a third voltage to a gate of a second unselected memory cell; and repeating the programming while stepping up the first voltage and stepping down the second voltage; wherein the first unselected memory cell is adjacent to the selected memory cell. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification
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Current AssigneeKioxia Corporation
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Original AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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InventorsMaejima, Hiroshi
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Primary Examiner(s)Pham, Ly D
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Application NumberUS13/424,658Publication NumberTime in Patent Office756 DaysField of Search365/185.02, 365/185.17, 365/185.19US Class Current365/185.19CPC Class CodesG11C 11/5621 using charge storage in a f...G11C 11/5628 Programming or writing circ...G11C 16/04 using variable threshold tr...G11C 16/0483 comprising cells having sev...G11C 16/10 Programming or data input c...G11C 16/107 Programming all cells in an...G11C 16/3427 Circuits or methods to prev...G11C 2213/75 Array having a NAND structu...H10B 43/27 the channels comprising ver...
