Packet based ID generation for serially interconnected devices

• US 8,700,818 B2
• Filed: 09/29/2006
• Issued: 04/15/2014
• Est. Priority Date: 09/29/2006
• Status: Expired due to Fees

• Current Assignee: NovaChips Canada Inc. (NovaChips Co., Ltd.)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Pyeon, Hong Beom, Oh, HakJune
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): Shyu, Jing-Yih
• Application Number:
  US11/529,293
• Publication Number:
  US 20080080492A1
• Time in Patent Office: 2,755 Days
• Field of Search: None
• US Class Current: 710/25
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory devices. The IDs are generated synchronously with clock. Command data and previously generated ID data are synchronously registered. The registered data is synchronously output and provided as parallel data for calculation of a new ID for the neighboring device. The calculation is an addition or subtraction by one. The IDs are generated in a packet basis by interpreting serial packet-basis commands received at the serial input in response to clocks. A clock latency is controlled in response to the interpreted ID and the clock. In accordance with the controlled clock latency, a new ID is provided in a packet basis. In high frequency generation applications (e.g., 1 GHz), two adjacent devices connected in daisy chain fashion are guaranteed enough time margin to perform the interpretation of packet commands.

Claims

1. An apparatus comprising a plurality of devices in a serial interconnection configuration, each of the plurality of devices having input and output connections, the serial interconnection configuration including at least first and second devices, the output connection of the first device being coupled to the input connection of the second device, the first device comprising:

a packet based processor comprising a clock producer responsive to an input clock to produce first and second clocks at different times, the packet based processor being configured;

to receive a first packet containing at least one packet start bit, an operation command for device identification production and a first device identifier number;

to interpret the operation command contained in the received first packet in synchronization with the first clock;

to produce a second device identifier number based on the first device identifier number in response to the at least one packet start bit contained in the received first packet and the interpreted operation command in synchronization with the second clock; and

to transfer a second packet containing the second device identifier number to the second device in synchronization with the input clock.

2. The apparatus of claim 1, wherein the packet based processor of the first device further comprises:

an input circuit for receiving the first packet through the input connection; and

an output circuit for outputting the second packet through the output connection to the second device.

3. The apparatus of claim 2, wherein the packet based processor of the first device further comprises:

an interpreter for interpreting the operation command contained in the first packet received through the input connection to provide the interpreted operation command.

4. The apparatus of claim 3, wherein the packet based processor of the first device further comprises:

a device identification producer for performing a calculation based on the first device identification number to produce the second device identification number in accordance with the interpreted operation command.

5. The apparatus of claim 4, wherein the device identification producer comprises:

a calculator for adding a predetermined increment value to the first device identification number to provide the second device identification number.

6. The apparatus of claim 4, wherein the device identification producer comprises:

a calculator for subtracting a predetermined decrement value to the first device identification number to provide the second device identification number.

7. The apparatus of claim 1, wherein the first device further comprises:

a device controller for controlling a clock latency of the first packet in response to the input clock and a clock latency control signal to control the clock latency of the output of the second packet such that there is a time gap between receiving the first packet and the transmission of the second packet.

8. The apparatus of claim 7, wherein the device controller comprises:

a clock delay element including a series-connected selectable time delay circuits; and

a selector for selecting a combination of the selectable time delay circuits, in response to the latency control signal.

9. The apparatus of claim 8, wherein the device controller further comprises:

at least one clock delay element that does not require selection and introduces a fixed delay.

10. The apparatus of claim 7, further comprising:

a controller configured to control operation of the serial interconnection of the devices, the controller providing the latency control signal.

11. The apparatus of claim 1, wherein each of the plurality of devices comprises a memory for storing data.

12. The apparatus of claim 11, wherein each of the plurality of devices includes a DRAM, an SRAM or flash memory.

13. The apparatus of claim 1, wherein the packet based processor of the first device further comprises an assignor for assigning either of the first device identification number contained in the first packet or the produced second device identification number as a device identification of that device.

14. The apparatus of claim 13, wherein the packet based processor of the first device further comprises a register for storing the assigned device identification number of that device.

15. A method for producing a device identifier in a serial interconnection configuration including a plurality of devices in a serial interconnection configuration, each of the plurality of devices having input and output connections, the serial interconnection configuration including at least first and second devices, the output connection of the first device being coupled to the input connection of the second device, the method comprising:

producing first and second clocks at different times in response to an input clock;

receiving a first packet containing at least one packet start bit, an operation command and a first device identifier number;

interpreting the received operation command to produce an interpreted operation command in synchronization with the first clock;

producing a second device identifier number based on the first device identifier number in response to the at least one packet start bit contained in the received first packet and the interpreted operation command in synchronization with the second clock; and

transferring a second packet containing the second device identifier number to the second device in synchronization with the input clock.

16. The method of claim 15, wherein the producing a second device identifier number comprises:

performing a calculation based on the first device identification number to produce the second device identification number in accordance with the interpreted operation command.

17. The method of claim 16, wherein the performing a calculation comprises:

adding a predetermined increment value to the first device identification number to provide the second device identification number.

18. The method of claim 16, wherein the step of interpreting comprises:

subtracting a predetermined decrement value to the first device identification number to provide the second device identification number.

19. The method of claim 15, further comprising:

controlling a clock latency in response to the first packet and the clock to provide a clock latency control signal, the clock latency control signal controlling the output of the second packet such that there is a time gap between receiving the first packet and the transmission of the second packet.

20. The method of claim 16, further comprising:

assigning either of the first device identification number contained in the first packet or the produced second device identification number as a device identification of that device.

21. The method of claim 20, further comprising:

storing the assigned device identification number of that device.