Computer system and abnormality detection circuit

• US 8,700,835 B2
• Filed: 12/04/2009
• Issued: 04/15/2014
• Est. Priority Date: 12/12/2008
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Nanri, Yousuke, Kume, Takayuki
• Primary Examiner(s): Myers, Paul R
• Application Number:
  US12/631,445
• Publication Number:
  US 20100153602A1
• Time in Patent Office: 1,593 Days
• Field of Search: 714/23, 714/56, 710/110
• US Class Current: 710/110
• CPC Class Codes: G06F 13/4226 with asynchronous protocol

Abstract

A computer system includes multiple modules that perform communication via a bus, and abnormality detection circuits that monitor signals on the bus related to communication between the modules to detect a hang-up, wherein each of the abnormality detection circuits is arranged to correspond to a part of the multiple modules, and, when detecting the hang-up, generates and outputs a signal instructing reactivation only of the corresponding module.

Claims

1. A computer system, comprising:

a plurality of modules configured to perform communication via a first bus; and

a plurality of abnormality detection circuits configured to monitor signals on the bus related to communication between the plurality of modules to detect a hang-up, wherein each of the abnormality detection circuits is connected between the first bus and a corresponding module; and

a hazard module configured to connect with and receive hang-up detection signals from each of the plurality of abnormality detection circuits via a second bus;

wherein when an abnormality detection circuit detects the hang-up, the abnormality detection circuit issues a response, via the first bus, to access requests from one or more of the plurality of modules, and the computer system is configured to monitor the hazard module to generate and output a signal instructing a reactivation only of the corresponding module while avoiding an initialization of the remaining plurality of modules based on the received hang-up detection signals via the second bus.

2. The computer system according to claim 1, wherein the abnormality detection circuit is configured to detect the hang-up if a state in which no response from the corresponding module to a request continues for a predetermined period in the communication between the modules.

3. The computer system according to claim 2, wherein the abnormality detection circuit has a register configured to set the predetermined period for detecting the hang-up.

4. The computer system according to claim 1, wherein the abnormality detection circuit has a register configured to represent that the hang-up has been detected.

5. The computer system according to claim 1, wherein the abnormality detection circuit has a register configured to set whether or not to output a reset signal or an interrupt signal when the hang-up is detected.

6. The computer system according to claim 1, wherein the abnormality detection circuit has a register configured to set the kind of the response returned by the response circuit.

7. The computer system according to claim 1, wherein the hazard module comprises a register configured to represent hang-up occurrences in the system as a list on the basis of a result of hang-up detection in each of the abnormality detection circuits.

8. The computer system according to claim 1, wherein one abnormality detection circuit is independently arranged for each of the modules.

9. The computer system according to claim 1, wherein at least one abnormality detection circuit is arranged to correspond to a module group including two or more of the modules.

10. The computer system according to claim 1, wherein the abnormality detection circuits are arranged for the slave-side modules among the multiple modules.

11. The computer system according to claim 1, wherein the abnormality detection circuits are arranged for the master-side modules among the multiple modules.

12. The computer system according to claim 1, wherein a signal instructing reactivation of the module is generated and outputted outside the abnormality detection circuit.

13. An abnormality detection circuit which is included in a computer system, the computer system having a plurality of modules that perform communication via a first bus for detecting a hang-up for a corresponding module among the plurality of modules, and a hazard module configured to connect with and receive hang-up detection signals from each of the plurality of abnormality detection circuits via a second bus, the abnormality detection circuit comprising:

a detection circuit connected between the bus and the corresponding module configured to monitor signals on the bus related to communication between the plurality of modules to detect a hang-up of the corresponding module; and

a signal generation circuit configured to, when the hang-up is detected by the detection circuit, issue a response to access requests from one or more of the plurality of modules,

wherein computer system is configured to monitor the hazard module to generate and output a signal instructing a reactivation only of the corresponding module while avoiding an initialization of the remaining plurality of modules based on the received hang-up detection signals via the second bus;

wherein the detection circuit detects the hang-up if no response from the corresponding module to a request continues for a predetermined period in the communication between the modules.

14. The abnormality detection circuit according to claim 13, further comprising a register configured to set the predetermined period for the detection of the hang-up.

15. The abnormality detection circuit according to claim 13, further comprising a register configured to represent that the hang-up of the corresponding module has been detected.

16. The abnormality detection circuit according to claim 13, further comprising a register configured to set whether or not to output a reset signal or an interrupt signal when the hang-up of the corresponding module is detected.

17. The abnormality detection circuit according to claim 13, further comprising a register configured to set the kind of the response returned by the response circuit.