Nonvolatile memory with write cache having flush/eviction methods
First Claim
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1. A nonvolatile memory, comprising:
- an array of memory cells organized into a plurality of blocks, each block being a plurality of memory cells that are erasable together;
said array of memory cells being partitioned into a first group of blocks and a second group of blocks;
a group of read/write circuits for reading or programming in parallel a corresponding page of memory cells among said array of memory cells;
said first group of blocks having first-group pages of memory cells that are each once programmable in between erasure, and each of the memory cells in the first-group pages storing one or more bit of data;
said second group of blocks having second-group pages of memory cells that are each multi-time programmable with a partial page of memory cells being once programmable each time, and each of the memory cells in the second-group page storing one bit of data; and
a cache memory configured from said second group of blocks to cache data being written in granularity of one or more partial page of memory cells, said cache memory archiving selected data to said first group of blocks as a function of predefined attributes of the selected data and predefined states of said first group of blocks and said second group of blocks.
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Abstract
A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to archive data from the cache memory to the main memory depend on the attributes of the data to be archived, the state of the blocks in the main memory portion and the state of the blocks in the cache portion.
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Citations
24 Claims
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1. A nonvolatile memory, comprising:
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an array of memory cells organized into a plurality of blocks, each block being a plurality of memory cells that are erasable together; said array of memory cells being partitioned into a first group of blocks and a second group of blocks; a group of read/write circuits for reading or programming in parallel a corresponding page of memory cells among said array of memory cells; said first group of blocks having first-group pages of memory cells that are each once programmable in between erasure, and each of the memory cells in the first-group pages storing one or more bit of data; said second group of blocks having second-group pages of memory cells that are each multi-time programmable with a partial page of memory cells being once programmable each time, and each of the memory cells in the second-group page storing one bit of data; and a cache memory configured from said second group of blocks to cache data being written in granularity of one or more partial page of memory cells, said cache memory archiving selected data to said first group of blocks as a function of predefined attributes of the selected data and predefined states of said first group of blocks and said second group of blocks. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. In a nonvolatile memory having an array of memory cells organized into a plurality of blocks, each block being a plurality of memory cells that are erasable together;
- a method of operating the nonvolatile memory, comprising;
partitioning the array of memory cells into a first group of blocks and a second group of blocks; providing a group of read/write circuits for reading or programming in parallel a corresponding page of memory cells among said array of memory cells; said first group of blocks having first-group pages of memory cells that are each once programmable in between erasure, and each of the memory cells in the first-group pages storing one or more bit of data; said second group of blocks having second-group pages of memory cells that are each multi-time programmable with a partial page of memory cells being once programmable each time, and each of the memory cells in the second-group page storing one bit of data; and archiving selected data from said second group of blocks to said first group of blocks as a function of predefined attributes of the selected data and predefined states of said first group of blocks and said second group of blocks. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
- a method of operating the nonvolatile memory, comprising;
Specification
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Current AssigneeSanDisk Technologies LLC (Western Digital Corporation)
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Original AssigneeSandisk Technologies Incorporated (Western Digital Corporation)
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InventorsPaley, Alexander, Gorobets, Sergey Anatolievich, Zilberman, Eugene, Bennett, Alan David, Traister, Shai, Tomlin, Andrew, Wu, William S., So, Bum Suck
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Primary Examiner(s)PATEL, KAUSHIKKUMAR M
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Application NumberUS12/348,895Publication NumberTime in Patent Office1,926 DaysField of SearchNoneUS Class Current711/103CPC Class CodesG06F 12/0246 in block erasable memory, e...G06F 12/0804 with main memory updating G...G06F 12/0866 for peripheral storage syst...G06F 2212/7203 Temporary buffering, e.g. u...G06F 2212/7204 Capacity control, e.g. part...G11C 11/5628 Programming or writing circ...G11C 2211/5641 Multilevel memory having ce...Y02D 10/00 Energy efficient computing,...
