Daisy chaining nonvolatile memories

• US 8,700,845 B1
• Filed: 08/12/2009
• Issued: 04/15/2014
• Est. Priority Date: 08/12/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bowers, Stephen Wilbur, Edgington, Joseph Douglas
• Primary Examiner(s): Bradley, Matthew
• Assistant Examiner(s): BERNARD, DANIEL J
• Application Number:
  US12/539,771
• Time in Patent Office: 1,707 Days
• Field of Search: None
• US Class Current: 711/110
• CPC Class Codes: G11C 7/1003 Interface circuits for daisy chain or ring bus memory arrangements
• CPC Class Codes: H04L 12/6418 Hybrid transport

Abstract

A host accessing memory devices by providing common address and command information on a parallel-connected serial bus to each of the memory devices and shifting data in the memory devices through a daisy-chain serial interface.

Claims

1. A system having a plurality of memory devices, the system comprising:

a first memory device and a second memory device of the plurality of memory devices;

a first shift register of the first memory device to receive serial address and command information at a first memory input pin of the first memory device, the first shift register being configured to couple in parallel to a first shift register of the second memory device and first shift registers of any other remaining memory devices of the plurality of memory devices to receive serial address and command information in parallel with the first shift register of the first memory device; and

a second shift register of the first memory device to receive data only at a second memory input pin of the first memory device and shift the data to provide shifted data at a memory output pin of the first memory device, the shifted data from the memory output pin to be communicated to a second shift register of the second memory device.

2. The system of claim 1, wherein the memory input pin and the memory output pin are coupled to other memory devices to form a serial daisy-chain.

3. The system of claim 1, wherein the serial address and command information is configured to be received on a serial bus coupled in parallel that couples to each of the plurality of memory devices to circumvent pipeline timing delays.

4. The system of claim 1, wherein the memory is a Phase-Change Memory (PCM) device.

5. The system of claim 1, wherein the memory is a Conductive-Bridging Random Access Memory (CBRAM) device.

6. The system of claim 1, wherein the memory is a Ferroelectric Random Access Memory (FRAM) device.

7. The system of claim 1, wherein the first shift register and the second shift register are part of a Serial Peripheral Interface (SPI).

8. A memory card, comprising:

a serial memory controller to provide an interface to a plurality of memory devices, the serial memory controller including an address and command bus, and a serial data output bus;

a first memory device of the plurality of memory devices having a first shift register coupled to the address and command bus and a second shift register having an input coupled to the serial data output bus of the serial memory controller; and

a second memory device of the plurality of memory devices having a first shift register coupled in parallel with the first shift register of the first memory device to the address and command bus and a second shift register having an input serially coupled to an output of the second shift register of the first memory device, an output of the second shift register being configured to provide a shifted serial data output of the second memory device.

9. The memory card of claim 8, wherein the address and command bus is a serial bus coupled in parallel that couples to other memory devices to circumvent pipeline timing delays.

10. The memory card of claim 8, wherein the second shift register of the first memory device and the second shift register of the second memory device are coupled in a serial daisy-chain.

11. A memory card, comprising:

a serial memory controller to provide an interface to memory devices, the serial memory controller including an address and command bus, and a serial data output bus;

a first memory device having a first multiplexer with a first input to receive serial information from the address and command bus and a second input to receive serial data from the serial data output from the serial memory controller, an output of the first multiplexer being coupled to a shift register in the first memory device; and

a second memory device having a second multiplexer with a first input coupled in parallel with the first input of the first multiplexer, the first input of the second multiplexer to receive the serial information from the address and command bus, the second multiplexer further having a second input to receive an output from the shift register in the first memory device, an output of the second multiplexer being coupled to a shift register in the second memory device.

12. The memory card of claim 11, wherein the shift register in the first memory device is configured to receive either an address or a command from the address and command bus during a first time period and to receive data from the serial data output in a second time period subsequent to the first time period.

13. The memory card of claim 11, wherein the shift register in the second memory device is configured to receive either an address or a command from the address and command bus during a first time period and to receive data from the output of the shift register in the first memory device in a second time period.