Optimizing power usage by factoring processor architectural events to PMU

• US 8,700,933 B2
• Filed: 03/06/2013
• Issued: 04/15/2014
• Est. Priority Date: 12/29/2006
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Liu, Yen-Cheng, Or, P Keong, Sistla, Krishnakanth, Srinivasa, Ganapati
• Primary Examiner(s): Abbaszadeh, Jaweed A
• Application Number:
  US13/787,085
• Publication Number:
  US 20130254572A1
• Time in Patent Office: 405 Days
• Field of Search: 713/300, 713/320, 713/322, 713/323, 713/324, 713/600
• US Class Current: 713/320
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 15/80 comprising an array of processing units with common control, e.g. single instruction multiple data processors G06F15/82 takes precedence ; for correlation function computation G06F17/15
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

Claims

1. A processor comprising:

a plurality of cores;

logic circuitry to detect whether one of a plurality of architectural events has occurred within one of the plurality of cores;

a plurality of thermal sensors of a first core to provide thermal data for the first core;

a plurality of counters of the first core each to count a number of occurrences of one of the architectural events;

a bus to couple the plurality of counters and the plurality of thermal sensors; and

a power control unit to modify a power state of one of the plurality of cores in response to occurrence of one of the architectural events.

2. The processor of claim 1, wherein the plurality of counters includes public counters and private counters.

3. The processor of claim 2, wherein the power control unit is to determine whether to modify the power state of one of the plurality of cores based on the occurrence values of at least some of the plurality of counters.

4. The processor of claim 1, wherein the bus includes a plurality of branches and wherein each branch is to monitor each of the plurality of counters in a designated time slot.

5. The processor of claim 1, wherein the bus is to send the data collected from each of the plurality of counters to the power control unit.

6. The processor of claim 1, wherein the power control unit is to manage thermal and power events for the first core, the power control unit further to receive the thermal data from the plurality of thermal sensors.

7. The processor of claim 1, wherein the logic circuitry is to initiate a power up sequence responsive to a count of at least one of the plurality of counters and to determine that a turbo mode is available.

8. The processor of claim 1, wherein the logic circuitry is to initiate a power down sequence responsive to a count of at least one of the plurality of counters.

9. The processor of claim 1, wherein the logic circuitry is to detect a core execution condition that an operating system (OS) cannot detect.

10. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

generating a signal to indicate an occurrence of an architectural event at a core of a multicore processor, wherein the architectural event is to be monitored by a channel of the core, wherein information corresponding to the architectural event is programmed into a state configured in the channel;

communicating the signal to a power control unit of the multicore processor via a bus shared with thermal sensor circuitry of the multicore processor; and

causing a power sequence based on the occurrence of the architectural event, wherein the power control unit is to determine whether to modify a power state of the core based on values of a plurality of counters each corresponding to an architectural event.

11. The non-transitory machine-readable medium of claim 10, wherein the method includes causing a power up sequence responsive to a first counter value, including powering up the core if reserve power is available, and causing a power down sequence responsive to a second counter value, including powering down the core.

12. The non-transitory machine-readable medium of claim 11, wherein causing the power up sequence comprises remaining idle if no reserve power is available.

13. The non-transitory machine-readable medium of claim 10, wherein the plurality of counters includes a counter to indicate a number of instructions retired per cycle, a counter to indicate a number of branch mispredictions during a time period in the core, a counter to indicate a number of translation lookaside buffer (TLB) misses during a time period in the core, and a counter to indicate a number of cache misses during a time period in the core.

14. A system comprising:

a processor including logic circuitry to detect whether an architectural event has occurred within a core using a channel of the core, based on information corresponding to the architectural event programmed into a state configured in the channel, a plurality of counters each to count a number of occurrences of one of a plurality of architectural events, a bus to couple the plurality of counters, and a power control unit to cause a power sequence in response to occurrence of one of the plurality of architectural events, wherein the power control unit is to determine whether to modify a power state of the core based on values of at least some of the plurality of counters; and

a dynamic random access memory (DRAM) coupled to the processor.

15. The system of claim 14, wherein the plurality of counters include a counter to indicate a number of cache misses during a time period in the core, the number of cache misses to indicate whether a corresponding program is to have access to a higher bandwidth on a system interconnect.

16. The system of claim 14, wherein the power control unit is to increase a frequency of the core if each of the plurality of counters is below a corresponding count threshold and to decrease the core frequency if one of the plurality of counters corresponding to cache misses is greater than a corresponding count threshold.

17. The system of claim 14, further comprising a plurality of thermal sensors to provide thermal data for the core, wherein the bus is to couple the plurality of counters and the plurality of thermal sensors.

18. The system of claim 17, wherein the power control unit is to make a power control decision for the core coherently based on the values of the at least some of the plurality of counters and values of a plurality of thermal sensors of the core.