Adaptive ultra-low voltage memory

• US 8,700,972 B2
• Filed: 11/04/2011
• Issued: 04/15/2014
• Est. Priority Date: 08/17/2011
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Penzes, Paul, Fullerton, Mark, Hukkoo, Ajat, Walley, John
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US13/289,691
• Publication Number:
  US 20130117626A1
• Time in Patent Office: 893 Days
• Field of Search: 714/701, 714/758, 714/763
• US Class Current: 714/758
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/601 Reconfiguration of cache memory
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
• CPC Class Codes: H03M 13/3715 Adaptation to the number of estimated errors or to the channel state
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments provide an adaptive memory that allows for low voltage modes of operation. In the low voltage modes of operation, the supply voltage provided to the memory is reduced below Vcc(min), which allows for significant savings in the power consumption of circuit components (e.g., the CPU) whose minimum voltage is dictated by Vcc(min). According to further embodiments, the memory can be configured dynamically according to various configurations depending on desired power savings (e.g., target Vcc(min)) and/or performance requirements (e.g., reliability, cache size requirement, etc.).

Claims

1. A computer system, comprising:

a power management unit (PMU);

a memory management unit (MMU); and

a central processing unit (CPU) chip comprising a CPU and a memory having a plurality of ways,

wherein the CPU is configured to determine a scheduled mode of operation of the computer system, and

wherein the MMU is configured to receive a control signal from the PMU, the control signal indicating the scheduled mode of operation of the computer system, to determine, responsive to the scheduled mode of operation a ratio of data ways to error correction code (ECC) ways of the plurality of ways, and to configure the memory according to determined ratio.

2. The computer system of claim 1, wherein the PMU is configured to provide a supply voltage to the memory.

3. The computer system of claim 2, wherein the scheduled mode of operation is a low power/performance mode of the computer system, and wherein the supply voltage is lower than a predetermined minimum supply voltage of the memory during the scheduled mode of operation.

4. The computer system of claim 3, wherein the predetermined minimum supply voltage of the memory is determined by a voltage below which a first bitcell failure occurs in the memory.

5. The computer system of claim 2, wherein the scheduled mode of operation is a normal mode of the computer system, and wherein the supply voltage is at least equal to a predetermined minimum supply voltage of the memory during the scheduled mode of operation.

6. The computer system of claim 1, wherein the memory is a cache memory.

7. The computer system of claim 6, wherein the scheduled mode of operation is a low power/performance mode of the computer system, and wherein the MMU configures each of the plurality of ways as a data way or an ECC way, wherein the data way is designated to store data and the ECC way is designated to store error correcting code for data stored in data ways.

8. The computer system of claim 7, wherein the MMU configures at least one way of the plurality of ways as an ECC way and designates the at least one way to store error correcting code for more than one data way.

9. The computer system of claim 7, wherein the MMU configures at least one way of the plurality of ways as an ECC way and designates the at least one way to store error correcting code for only one data way.

10. The computer system of claim 9, wherein the only one data way is designated to store data of high priority.

11. The computer system of claim 7, wherein the MMU is configured to determine, for each of the plurality of ways configured as an ECC way, a type/rate of error correcting code based on the scheduled mode of operation.

12. The computer system of claim 6, wherein the scheduled mode of operation is a normal mode of the computer system, and wherein the MMU configures each of the plurality of ways as a data way, thereby configuring the cache memory for a maximum cache size.

13. The computer system of claim 6, wherein the plurality of ways include a first way designed for low supply voltage operation and a second way designed for normal supply voltage operation.

14. The computer system of claim 13, wherein the scheduled mode of operation is a low power/performance mode of the computer system, and wherein the MMU configures the first way to be ON and the second way to be OFF during the scheduled mode of operation.

15. The computer system of claim 13, wherein the scheduled mode of operation is a normal mode of the computer system, and wherein the MMU configures both the first way and the second way to be ON during the scheduled mode of operation.

16. The computer system of claim 6, wherein the scheduled mode of operation is a low power/performance mode of the computer system, and wherein the MMU configures at least one of the plurality of ways from a write-back write policy to a write-through write policy.

17. A computer system, comprising:

a power management unit (PMU);

a memory management unit (MMU); and

a memory having a plurality of ways,

wherein the MMU is configured to receive a control signal from the PMU, the control signal indicating at least one of a memory size requirement and a desired hit/miss rate of the memory, and to configure the memory responsive to the control signal.

18. A computer system, comprising:

a power management unit (PMU);

a memory management unit (MMU); and

a memory having a plurality of ways,

wherein the MMU is configured to receive a control signal from the PMU, the control signal indicating a scheduled mode of operation of the computer system, and to configure the memory according to the scheduled mode of operation of the computer system, and

wherein, when the scheduled mode of operation is a low power/performance mode of the computer system, the MMU is further configured to partition at least one way of the plurality of ways of the memory between data bits and error correction code (ECC) bits.

19. The computer system of claim 18, wherein the partition is adjusted dynamically based on one or more of:

a supply voltage provided to the memory and an error correcting code of the ECC bits.