Design, layout, and manufacturing techniques for multivariant integrated circuits

• US 8,701,057 B2
• Filed: 04/11/2011
• Issued: 04/15/2014
• Est. Priority Date: 04/11/2011
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Kelleher, Brian
• Primary Examiner(s): LEVIN, NAUM B
• Application Number:
  US13/084,364
• Publication Number:
  US 20120258579A1
• Time in Patent Office: 1,100 Days
• Field of Search: 716 54- 56, 716/119
• US Class Current: 716/56
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

An integrated circuit (IC) is designed that includes one variant having a plurality of a modular circuits communicatively coupled together and a second variant having a sub-set of the plurality of modular circuits. The modular circuits are then laid out on a wafer for fabricating each of the variants of the IC. The layout includes routing communicative couplings between the sub-set of the modular circuits of the second variant to the other modular circuits of the first variant in one or more metallization layers to be fabricated last. Fabricating the IC is then started, up to but not including the one or more metallization layers to be fabricated last. One or more of the plurality of variants of the IC is selected based upon a demand predicted during fabrication. Fabrication then continues with the last metallization layers of the IC according to the selected layout.

Claims

1. A method comprising:

predicting an initially demand for each of a plurality of selectable grouping of a modular circuit of an integrated circuit prior to fabricating the integrated circuit;

designing the integrated circuit including the plurality of selectable groupings of a modular circuit based upon the predicted initial demand;

laying out the designed integrated circuit including scribe boundaries between particular groupings of the modular circuit, and routing the interconnects and vias between modular circuits that cross the scribe boundaries between the particular groupings of the modular circuit in the last one or more metallization layers to be fabricated;

fabricating the integrated circuit on one or more wafers accordingly to the layout up to but not including fabricating the interconnects and vias;

predicting a revised demand for each of the plurality of selectable groupings of the modular circuit during fabrication of the integrated circuit up to but not including the interconnects and vias;

selecting one or more of the plurality of groupings of the modular circuit based upon the predicted revised demand;

fabricating a subset of the interconnects and vias of the integrated circuit according to the layout of the selected one or more groupings of the modular circuit; and

singulating the wafer into a plurality of integrated circuit die according to the layout of the selected one or more groupings of the modular circuit.

2. The method according to claim 1, wherein the modular circuit comprises one or more processor cores and one or more associated peripheral circuits.

3. The method according to claim 1, wherein predicting the revised demand comprises a market analysis of each of the plurality of selectable groupings of the modular circuit.

4. The method according to claim 1, further comprising:

estimating a yield for each of the plurality of selectable groupings of the modular circuit during fabrication of the integrated circuit up to but not including the interconnects and vias; and

selecting the one or more of the plurality of groupings of the modular circuit further based upon the estimated yield.

5. The method according to claim 1, further comprising fabricating the integrated circuit on one or more wafers according to the layout and the predicted initial demand up to but not including the interconnects and vias.

6. The method according to claim 1, further comprising:

analyzing a market to identify one or more attributes selected, from a group consisting of one or more product features, one or more performance metrics, one or more target costs, and the initial demand; and

designing the integrated circuit including the plurality of selectable groupings of a modular circuit based on the market analysis.

7. The method according to claim 1, further comprising:

analyzing a market to identify one or more attributes selected from a group consisting of one or more product features, one or more performance metrics, one or more target costs, and the initial demand; and

laying out the integrated circuit based on the market analysis.

8. The method according to claim 1, wherein the integrated circuit includes a first set of modular circuits including a first processor core and a second set of modular circuits including a second processor core, wherein the first processor core and second processor core are different and the first and second modular circuits may be combined in selectable groupings.