Methods, systems, and articles of manufactures for implementing electronic circuit designs with IR-drop awareness

• US 8,701,067 B1
• Filed: 07/22/2011
• Issued: 04/15/2014
• Est. Priority Date: 07/24/2010
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: McSherry, Michael, Yanagida, Bruce, Fischer, Ed, White, David, Krishnan, Prakash
• Primary Examiner(s): LEVIN, NAUM B
• Application Number:
  US13/189,274
• Time in Patent Office: 998 Days
• Field of Search: 716110-112, 716/115, 716/132, 716/136
• US Class Current: 716/112
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Disclosed are a method, system, and computer program product for implementing electronic circuit designs with IR-drop awareness. Some embodiments perform schematic level simulation(s) to determine electrical characteristics, identifies physical parasitics of a layout component, determines the electrical or physical characteristics associated to IR-drop analysis on the component, and determines whether the component meets IR-drop related constraint(s) while implementing the physical design of the electronic circuit in some embodiments. Some embodiments further determine adjustment(s) to the component or related data where the IR-drop related constraints are not met and/or and present the adjustment(s) in the form of hints. Various data and information, such as currents in various forms or voltages, are passed between various schematic level tools and physical level tools.

Claims

1. A computer implemented method for implementing an electronic circuit design with IR-drop awareness, comprising:

prior to completing an incomplete net of the electronic circuit design, using at least one processor to perform a process, the process comprising;

identifying, determining, or updating physical data of a component that is situated along the incomplete net in an incomplete physical design of the electronic circuit design;

characterizing an electrical parasitic that is associated with the physical data of the component by at least assembling one or more pieces of electric current information or one or more voltages in a schematic domain, rather than in a physical domain to which the incomplete physical design belongs; and

characterizing an electrical characteristic that is associated with the electrical parasitic and the physical data of the component while the component is being added or modified along the incomplete net of the electronic circuit design.

2. The computer implemented method of claim 1, the process further comprising:

displaying the electrical characteristic associated with the physical data of the component or storing the electrical characteristic in a non-transitory computer readable storage medium.

3. The computer implemented method of claim 1, the process further comprising:

identifying or determining an IR-drop related constraint that is associated with the electrical characteristic.

4. The computer implemented method of claim 3, the process further comprising:

ensuring correctness of the physical data or other data that are related to the IR-drop related constraint.

5. The computer implemented method of claim 4, the process further comprising:

determining an adjustment to the physical data or to the component based at least in part upon the IR-drop related constraint.

6. The computer implemented method of claim 5, the process further comprising:

determining whether the adjustment causes one or more violations of one or more design rules or one or more constraints other than the IR-drop related constraint.

7. The computer implemented method of claim 5, the process further comprising:

displaying a hint, which is based at least in part upon the adjustment, on a display apparatus or applying the adjustment to the physical data or to the component.

8. The computer implemented method of claim 7, the process further comprising:

iteratively determining whether the IR-drop related constraint or another IR-drop related constraint is met based at least in part upon an identification, determination, or update of the physical data after applying the adjustment to the physical data or the component.

9. The computer implemented method of claim 3, wherein the act of identifying or determining the IR-drop related constraint comprises:

checking the electrical characteristic against the IR-drop related constraint for the component based at least in part upon the electrical characteristic.

10. The computer implemented method of claim 1, wherein the act of characterizing the electrical characteristic that is associated with the electrical parasitic comprises:

performing simulation on the electronic circuit design to solve for one or more currents for the component; and

determining the electrical characteristic by using a solver.

11. The computer implemented method of claim 1, wherein the act of characterizing the electrical characteristic that is associated with the electrical parasitic comprises:

identifying or generating thermal data and a schematic of the electronic circuit design;

generating a netlist;

specifying one or more simulation parameters or one or more analysis points or corners;

performing a simulation to determine one or more electrical characteristics at a first level; and

determining the electrical characteristic at a second level based at least in part upon the one or more electrical characteristics at the first level and the electrical parasitic by using a solver.

12. The computer implemented method of claim 1, the process further comprising at least one of:

identifying thermal data for the component;

mapping data, which correspond to the physical data of the component, at a first level to a second level of the electronic circuit design;

reducing the electrical parasitic; and

specifying one or more simulation parameters or one or more analysis points or corners.

13. The computer implemented method of claim 1, wherein the act of characterizing the electrical characteristic that is associated with the electrical parasitic comprises:

mapping data, which correspond to the physical data of the component, at a second level to a first level of the electronic circuit design;

reducing the electrical parasitic to an approximate form;

specifying one or more simulation parameters or one or more analysis points or corners; and

performing a simulation at the second level to determine the electrical characteristic.

14. The computer implemented method of claim 1, the process further comprising:

identifying, determining, or updating the electrical characteristic, wherein the act of identifying, determining, or updating the electrical characteristic comprises;

receiving a user-provided electrical characteristic at a second level from a user; and

identifying, determining, or updating the electrical characteristic by performing a simulation based at least in part upon the user-provided electrical characteristic.

15. The computer implemented method of claim 1, the process further comprising:

performing simulation or re-simulation for the electronic circuit design based at least in part upon the electrical parasitic before the incomplete layout of the electronic circuit design is completed.

16. The computer implemented method of claim 15, the process further comprising:

matching a simulation parameter for the simulation or re-simulation with an extraction parameter that is used for extraction on the electronic circuit design;

stitching a form of the electrical parasitic into a schematic design of the electronic circuit design; and

identifying one or more parasitic-aware electrical characteristics for one or more electrical analyses.

17. The computer implemented method of claim 1, wherein the incomplete layout of the electronic circuit design does not pass a layout versus schematic check or verification.

18. The computer implemented method of claim 1, in which the act of characterizing the electrical parasitic comprises:

identifying where along at least a particular net to create a geometric description of the component is to be created; and

mapping the geometric description to an equivalent parasitic value.

19. The computer implemented method of claim 1, the process further comprising:

identifying a violation of a design requirement for the electrical characteristic; and

determining a hint that corresponds to at least a part of the physical data to resolve the violation.

20. The computer implemented method of claim 1, the process further comprising:

mapping the electrical characteristic between a schematic design of the electronic circuit design and at least the incomplete physical design of the electronic circuit design; and

assemble the electrical characteristic, which has been mapped, and provides one or more assembled electrical characteristics to a solver to solve for at least the incomplete physical design of the electronic circuit design.