Method for wafer-level testing diced multi-chip stacked packages

• US 8,703,508 B2
• Filed: 08/14/2012
• Issued: 04/22/2014
• Est. Priority Date: 08/14/2012
• Status: Expired due to Fees

• Current Assignee: Powertech Technology Inc
• Original Assignee: Powertech Technology Inc
• Inventors: Chang, Kai-Jun, Liu, Yu-Shin, Chen, Shin-Kung, Chan, Kun-Chih
• Primary Examiner(s): Luu, Chuong A
• Assistant Examiner(s): FORTICH, RODOLFO D
• Application Number:
  US13/585,102
• Publication Number:
  US 20140051189A1
• Time in Patent Office: 616 Days
• Field of Search: 438/15, 438/118, 438/127, 438/458, 438/462
• US Class Current: 438/15
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence

Abstract

Disclosed is a method for wafer-level testing a plurality of diced multi-chip stacked packages. Each package includes a plurality of chips with vertically electrical connections such as TSVs. Next, according to a die-on-wafer array arrangement, the multi-chip stacked packages are fixed on a transparent reconstructed wafer by a photo-sensitive adhesive, and the packages are located within the component-bonding area of the wafer. Then, the transparent reconstructed wafer carrying the multi-chip stacked packages can be loaded into a wafer tester for probing. Accordingly, the wafer testing probers in the wafer tester can be utilized to probe the testing electrodes of the stacked packages so that it is easy to integrate this wafer-level testing method especially into TSV packaging processes.

Claims

1. A method for wafer-level testing a plurality of diced multi-chip stacked packages, comprising the steps of:

providing the plurality of multi-chip stacked packages where each multi-chip stacked package includes a plurality of chips vertically stacked together and has a top surface, a bottom surface, and a plurality of testing electrodes disposed on the top surface;

fixing the multi-chip stacked packages on a transparent reconstructed wafer according to a die-on-wafer array arrangement wherein the transparent reconstructed wafer includes a plurality of component placement regions defined by a plurality of alignment marks and has a photosensitive adhesive adhered to the bottom surfaces of the multi-chip stacked packages to locate the multi-chip stacked packages within the component placement regions, wherein the transparent reconstructed wafer further has a barcode of wafer ID disposed at an edge of the transparent reconstructed wafer outside the component placement regions;

loading the transparent reconstructed wafer with the multi-chip stacked packages into a wafer tester;

using a plurality of probes of a probe card installed in the wafer tester to probe the testing electrodes to electrically test the multi-chip stacked packages; and

radiating light on the photosensitive adhesive through the transparent reconstructed wafer to pick up and sort out the multi-chip stacked packages.

2. The method as claimed in claim 1, wherein the transparent reconstructed wafer is a glass disc.

3. The method as claimed in claim 1, wherein the step of providing the multi-chip stacked packages includes the following sub-steps:

disposing a plurality of substrate-less chip-stacked cubes on an adhesive tape, each substrate-less chip-stacked cube consisting of the chips with a gap formed between the adjacent vertically stacked chips wherein the testing electrodes are relatively away from the adhesive tape; and

forming an encapsulation material on the adhesive tape to completely fill the gap between the adjacent vertically stacked chips.

4. The method as claimed in claim 3, wherein the step of providing the multi-chip stacked packages further includes the following sub-step:

removing a bleeding portion of the encapsulation material exceeding the footprints of the substrate-less chip-stacked cubes after forming the encapsulation material.

5. The method as claimed in claim 4, wherein the encapsulation material still encapsulates a plurality of sidewalls of the chips after removing the bleeding portion.

6. The method as claimed in claim 5, wherein the encapsulation material is a positive-photoresist type underfill, wherein the bleeding portion is removed by exposure and development of the encapsulation material.

7. The method as claimed in claim 4, wherein the adhesive tape is pre-disposed in an opening of a strip-type tape carrier to simulate a substrate strip before the step of disposing the substrate-less chip-stacked cubes on the adhesive tape.

8. The method as claimed in claim 1, wherein a plurality of through-silicon vias are disposed inside each chip and a plurality of micro bumps are disposed in the gap between the adjacent vertically stacked chips to electrically connect to the through-silicon vias.

9. The method as claimed in claim 8, wherein each multi-chip stacked package further has a plurality of external bumps disposed on the top surface.

10. The method as claimed in claim 1, wherein the alignment marks include a plurality of X-axes and a plurality of Y-axes without covering by the multi-chip stacked packages after fixing the multi-chip stacked packages on the transparent reconstructed wafer.

11. The method as claimed in claim 10, wherein the X-axes and the Y-axes extend to the peripheries of the transparent reconstructed wafer.

12. The method as claimed in claim 1, wherein the alignment marks include a plurality of central alignment marks corresponding to the component placement regions.

13. The method as claimed in claim 1, wherein the alignment marks include a plurality of corner alignment marks at the corners of the component placement regions.

14. The method as claimed in claim 1, wherein the alignment marks include a plurality of peripheral alignment marks within the component placement regions.

15. A method for wafer-level testing a plurality of diced multi-chip stacked packages, comprising the steps of:

providing the plurality of multi-chip stacked packages where each multi-chip stacked package includes a plurality of chips vertically stacked together and has a top surface, a bottom surface, and a plurality of testing electrodes disposed on the top surface;

fixing the multi-chip stacked packages on a transparent reconstructed wafer according to a die-on-wafer array arrangement wherein the transparent reconstructed wafer includes a plurality of component placement regions defined by a plurality of alignment marks and has a photosensitive adhesive adhered to the bottom surfaces of the multi-chip stacked packages to locate the multi-chip stacked packages within the component placement regions, wherein the alignment marks include a plurality of central alignment marks corresponding to the component placement regions;

loading the transparent reconstructed wafer with the multi-chip stacked packages into a wafer tester;

using a plurality of probes of a probe card installed in the wafer tester to probe the testing electrodes to electrically test the multi-chip stacked packages; and

radiating light on the photosensitive adhesive through the transparent reconstructed wafer to pick up and sort out the multi-chip stacked packages.