Method for forming a back-side illuminated image sensor with a junction insulation

• US 8,703,528 B2
• Filed: 04/12/2012
• Issued: 04/22/2014
• Est. Priority Date: 04/12/2011
• Status: Active Grant

• Current Assignee: Stmicroelectronics France (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV), STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Marty, Michel, Roy, Franois, Prima, Jens
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US13/445,199
• Publication Number:
  US 20120261670A1
• Time in Patent Office: 740 Days
• Field of Search: 438/57, 438/96, 257/57, 257/72, 257/292, 257/E31.043
• US Class Current: 438/96
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

A method for forming a back-side illuminated image sensor, including the steps of: a) forming, from the front surface, doped polysilicon regions, of a conductivity type opposite to that of the substrate, extending in depth orthogonally to the front surface and emerging into the first layer; b) thinning the substrate from its rear surface to reach the polysilicon regions, while keeping a strip of the first layer; c) depositing, on the rear surface of the thinned substrate, a doped amorphous silicon layer, of a conductivity type opposite to that of the substrate; and d) annealing at a temperature capable of transforming the amorphous silicon layer into a crystallized layer.

Claims

1. A method for forming a back-side illuminated image sensor from a semiconductor substrate comprising, stacked on each other, a first layer of a first doping level on the rear surface side, and a second layer of same conductivity type as the first layer but of lower doping level on the front surface side, this method comprising:

a) forming, from the front surface, doped polysilicon regions, of a conductivity type opposite to that of the substrate, extending in depth orthogonally to said front surface and emerging into the first layer;

b) thinning the substrate from its rear surface to reach the polysilicon regions, while keeping a strip of the first layer;

c) depositing, on the rear surface of the thinned substrate, a doped amorphous silicon layer, of a conductivity type opposite to that of the substrate; and

d) annealing at a temperature capable of transforming said amorphous silicon layer into a crystallized layer.

2. The method of claim 1, wherein, at step d), the anneal is performed in the same equipment as that used, at step c), for the deposition of said amorphous silicon layer.

3. The method of claim 1, wherein said temperature ranges between 350 and 450°

C.

4. The method of claim 1, wherein a thickness of the amorphous silicon ranges between 1 and 10 nm.

5. The method of claim 1, wherein the forming of said polysilicon regions comprises the opening of trenches in the substrate and the filling of these trenches with polysilicon, an intermediary step of implantation of dopant elements, of same conductivity type as the second layer but of higher doping level being provided after the etching of the trenches but before their filling.