Source and body contact structure for trench-DMOS devices using polysilicon
First Claim
1. A method for manufacturing a semiconductor device comprising:
- a) providing an N-type epitaxial (N-epi) layer;
b) forming a trench mask on top of the N-epi layer;
c) etching the N-epi layer through the trench mask to a predetermined depth to form a trench;
d) forming a gate oxide on a bottom and sidewalls of the trench;
e) filling a remaining space in the trench with a conductive material to form a gate electrode;
f) removing the trench mask;
g) implanting and diffusing dopants into a top region of the N-epi layer to form a P-body layer;
h) implanting and diffusing dopants into a top region of the P-body layer to form a source region;
i) forming oxide on top of the gate electrode and the source region;
j) etching portions of the oxide to expose selected portions of the source region;
k) etching selected portions of the source region not covered by the oxide down to the P-body layer;
l) depositing N+ doped polysilicon on sidewalls of remaining portions of the source region and the oxide; and
m) etching back the N+ doped polysilicon to form an N+ doped polysilicon spacer disposed along the sidewalls of the remaining portions of the source region and the oxide.
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Accused Products
Abstract
A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
22 Citations
10 Claims
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1. A method for manufacturing a semiconductor device comprising:
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a) providing an N-type epitaxial (N-epi) layer; b) forming a trench mask on top of the N-epi layer; c) etching the N-epi layer through the trench mask to a predetermined depth to form a trench; d) forming a gate oxide on a bottom and sidewalls of the trench; e) filling a remaining space in the trench with a conductive material to form a gate electrode; f) removing the trench mask; g) implanting and diffusing dopants into a top region of the N-epi layer to form a P-body layer; h) implanting and diffusing dopants into a top region of the P-body layer to form a source region; i) forming oxide on top of the gate electrode and the source region; j) etching portions of the oxide to expose selected portions of the source region; k) etching selected portions of the source region not covered by the oxide down to the P-body layer; l) depositing N+ doped polysilicon on sidewalls of remaining portions of the source region and the oxide; and m) etching back the N+ doped polysilicon to form an N+ doped polysilicon spacer disposed along the sidewalls of the remaining portions of the source region and the oxide. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for manufacturing a semiconductor device comprising:
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a) providing an epitaxial layer of a first polarity type semiconductor; b) forming a trench mask on top of the epitaxial layer; c) etching the epitaxial layer through the trench mask to a predetermined depth to form a trench; d) forming a gate oxide on a bottom and sidewalls of the trench; e) filling a remaining space in the trench with a conductive material to form a gate electrode; f) removing the trench mask; g) implanting and diffusing dopants into a top region of an opposite polarity type to that of the epitaxial layer into the epitaxial layer to form a body layer of an opposite polarity to that of the epitaxial layer; h) implanting and diffusing dopants into a top region of the body layer to form a source region; i) forming oxide on top of the gate electrode and the source region; j) etching portions of the oxide to expose selected portions of the source region; k) etching selected portions of the source region not covered by the oxide down to the body layer; l) depositing doped polysilicon on sidewalls of remaining portions of the source region and the oxide; and m) etching back the doped polysilicon to form a doped polysilicon spacer disposed along the sidewalls of the remaining portions of the source region and the oxide.
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Specification