Bottom-notched SiGe FinFET formation using condensation
First Claim
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1. A method of forming an integrated circuit structure, the method comprising:
- forming a silicon fin over a silicon substrate;
forming a silicon germanium layer on a top surface and sidewalls of the silicon fin;
forming an undercut in an insulation region directly underlying and contacting the SiGe layer to expose a sidewall of a silicon extension region directly underlying the silicon fin; and
performing a condensation to convert the silicon germanium layer and the silicon fin into a silicon germanium (SiGe) fin and a silicon oxide layer on a top surface and opposite sidewalls of the SiGe fin.
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Abstract
An integrated circuit structure includes a substrate and a germanium-containing semiconductor fin over the substrate. The germanium-containing semiconductor fin has an upper portion having a first width, and a neck region under the upper portion and having a second width smaller than the first width.
209 Citations
19 Claims
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1. A method of forming an integrated circuit structure, the method comprising:
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forming a silicon fin over a silicon substrate; forming a silicon germanium layer on a top surface and sidewalls of the silicon fin; forming an undercut in an insulation region directly underlying and contacting the SiGe layer to expose a sidewall of a silicon extension region directly underlying the silicon fin; and performing a condensation to convert the silicon germanium layer and the silicon fin into a silicon germanium (SiGe) fin and a silicon oxide layer on a top surface and opposite sidewalls of the SiGe fin. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of forming an integrated circuit structure, the method comprising:
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forming two insulation regions in a silicon substrate, with an extension portion of the silicon substrate between and adjoining the two insulation regions; recessing the two insulation regions, wherein a top part of the extension portion of the silicon substrate forms a silicon fin above remaining portions of the two insulation regions; epitaxially growing a silicon germanium (SiGe) layer on a top surface and sidewalls of the silicon fin; recessing the remaining portions of the two insulation regions to form an undercut under the SiGe layer; and performing a condensation to convert the SiGe layer into silicon oxide and the silicon fin into a SiGe fin, resulting in a silicon oxide layer on a top surface and sidewalls of the SiGe fin. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method of forming an integrated circuit structure, the method comprising:
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forming a silicon fin over a silicon substrate, the silicon fin extending from the silicon substrate; forming two insulation regions on opposite sides of the silicon fin, an extension portion of the silicon substrate between and adjoining the two insulation regions; epitaxially growing a silicon germanium (SiGe) layer on a top surface and sidewalls of the silicon fin; recessing the two insulation regions to form an undercut under the SiGe layer; and performing a condensation to convert the SiGe layer into silicon oxide and the silicon fin into a SiGe fin, resulting in a silicon oxide layer on a top surface and sidewalls of the SiGe fin, the SiGe fin comprising a top portion having a first width, and a neck region underlying the top portion and having a second width smaller than the first width. - View Dependent Claims (17, 18, 19)
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Specification